MiSTer FPGA Forum

Will there ever be (or is there already) a way to potentially "dual boot" the DE10 into either the MiSTer framework or any other framework, from the same storage device? Failing that, swapping out an SD card for a different framework is no problem anyway. I guess this may be a redundant question as the MiSTer framework is not just the SD...

The new board is based on Xilinx Ultrascale+ MPSoC. I've been working directly with Xilinx for some time. Layout was near complete with the 3EG, but it made sense to switch to the Kria module when that was released. I'll show where we are shortly. Aberu, the MDEC was complete and the SPU mostly in May. They were not committed to the original ps-fpg...

I know.
But how to use it on a "mister hardware". Mister is not just the de-10 nano There's the pins used for the memory and I/O...
Would booting it from a SD card work? I don't think so.

We've kept compatibility with mister SDRAM and the IO module (as this is what people have).
You just need to flash an sdcard with the image and swap.

A bit redundant now Rob is on the case. Laxer's core was in dev for years. It was parked in May at ~95% done. Laxer reached out to Robert to see if he wanted to collaborate, but Robert decided (and I do get this) to start his own. All good. I've been helping Laxer on and off for years and we decide to bring it up on the DE just to get it over the ...

Ah thanks! Your biggest problem will be any changes to the pinout etc will mean forking all the cores. I might be able to target your board with a new backend for my framework depending what memory choices you make. Send me an email.

MIkeJ (Replay2) here - I wish I could find a cheap module supplier for the ultrascale part, it would make my life so much easier!
Good choice with the Exor module - although have you considered the TSoM module that Terasic do as well?

Hi,
Sorry I wasn't asking for sponsorship, but if you feel you want to support the team later that's great.
The plan was always to make it open - our old SVN repository was and contains a lot of code that made it's way into Mister.
We've moved to github and it's taking some time to refactor, but it will be public again soon.
/Mike

Yes, both hybrid and RiscV based CPU cores are in development.

Hi. I do the FPGAArcade stuff. I opensourced the RTG code ahead of the full core, but it looks difficult to integrate. While I am fully focused on my upcoming Replay2 platform, it's (like nuclear fusion) always 2 months away. I had a beer with the team earlier and nobody objected to us making a build for the DE10-nano platform. Note, this is not a ...