MiSTer FPGA Forum

My main question regarding the sharing of the DDR3 memory between the FPGA and the ARM is this: at what point would a simulated CPU show latency issues? For example, the TMS9900 used in the 99/4A, was 3.3 MHz. There is an expanded memory option that boosted its memory to 1MB and there were GRAM devices too. All of which would exceed the on-board bl...