MiSTer FPGA Forum

Most of the changes I made to the Oric core earlier this year were in attempts to get TAP loading supported through the OSD. It required a bit of conversion to Verilog from VHDL in order to simulate the core on Verilator. My initial approach to parse the TAP format and bypass traditional cassette loading methods was getting too complicated so I we...

I have tried the tap and bios loader on the new core and they work great.
The only thing that seems broken is the disk controller. Neither sedoric4 nor large disk images work.
I have attached the latest version of Rampa's core (not yet published) in which the disk works fine.

Congratulations, the tap loader works great.
As an additional feature you would consider adding switching between qwerty and azerty keyboards.

I would be happy to try your work with macintosh .vhd files.