MiSTer FPGA Forum

If you are having trouble booting the core, please try the latest (unreleased) version.

Make sure you update the main menu core also.

And if you can please you let me know in the GitHub issue if it works/doesn't work for you: https://github.com/MiSTer-devel/Arcade- ... /issues/18

Sorry some folks are having trouble getting the core to run.

I just posted something about this on my Patreon (public post): https://www.patreon.com/posts/46222825

TL;DR I'm working on the boot issues for some people.

Thank you for turning your analog engineering skills at this issue, Jotego. I agree that this is something the community needs to figure out. I have no doubt that if we want to see the more modern arcade cores come to MiSTer, then we will need to be able to access the full bandwidth (~100MHz) of the SDRAM module. Sure you can do other tricks, like ...

Tecmo:

* Run Rygar CPU at 6MHz
* Fix layer DMA timing
* Add reset signal to PLL
* Tweak SDRAM phase shift

Glad to hear you figured it out.

Gryzor wrote: ↑Sat Jul 04, 2020 12:47 pm Edit: Never mind, just saw Josh has already managed to fix it

Yep, new release coming soon which should hopefully sort out any SDRAM-related memory issues (i.e. glitches).

A book that I am currently using and that I am finding very practical to use Verilog at the synthesized level, with many tips and practical examples is: https://www.amazon.es/FPGA-Prototyping-Verilog-Examples-Spartan-3-ebook/dp/B00HLHWWGA Although it is oriented to Xilinx FPGA, almost everything is applicable to an Altera FPGA. I have the VHDL ver...

Completely misleading conclusion. Compilation time depends on FPGA fabric and Quartus version. 1) Using Quartus 13 gives faster compilation time than Quartus 17, but support of Cyclone V in Q13 was preliminary and sometimes it produces misbehaving core. So Q13 is good for debug compilation, but releases should be compiled in Quartus 17. 2) Compili...

Beeble wrote: ↑Mon Jun 08, 2020 8:28 am Well, I would love a "Wardner no mori", my favourite non-shooter Toaplan game =)

Me too, I love that game.

Unfortunately it looks like there aren't any other games which run on that arcade hardware, so it's not good bang-for-buck in terms of development effort. But for classic games it's worth it

Coming from a large-scale C++ software development background, these iteration times are something I'll have to adjust to. Maybe it means I do a lot of work in Verilator first. It also seems like disabling HDMI support does substantially improve iteration time though? Yes, unfortunately long compile times are the norm with MiSTer cores. I have hea...

@nullobject, as this is Verilog and also the top Level of any Mister project is a Verilog .sv file ... do you think it is better to start with Verilog or with VHDL? I think you need to at least be familiar with Verilog/SystemVerilog and VHDL — but you only need to be proficient in one of these. It doesn't really matter which one. I find VHDL much ...

FPGAzumSpass wrote: ↑Tue Jun 02, 2020 4:36 pm The Framework is checked into the project, but i'm not sure if it still compiles after the latest folder restructure.

Sounds very interesting, I'll check it out.

Looks like a neat little game

Coming from the software world, I feel that proper testing is really missing from hardware projects. Yes you can create a test bench or use signal tap to help debug one-off issues, but IMHO what we really need is proper integration testing — i.e. tests that are run every time someone pushes a code change to GitHub. It's the only way to have a high ...

I can also recommend this book, which is a fairly gentle intro to arcade hardware in Verilog. It covers fundamental things like CPU, memory, video hardware, tilemaps, sprites, etc.

You can run their example code in your browser, which is nice for playing around with the concepts they cover.

I want to learn more about developing a MiSTer core. What would be the simplest core to review the source of? To build a core, first you should get a handle on some of the fundamentals (depending on your skill level). If you're completely new to FPGA development, start by blinking LEDs on/off, etc. A good book on VHDL and/or Verilog is highly reco...