MiSTer FPGA Forum

MicroCoreLabs

Yes, the prefetch queue is implemented the same as the real 8088. The music playing at the end of the 8088 MPH demo relies on the prefetch queue operating correctly and the PCXT core seems to run this fine. Also the tools which identify the processor type using the prefetch queue correctly identify the core as an 8088.

MicroCoreLabs

Well said... Implementing all of the protected-mode functionality is a heavy lift - but without all of this we are left with a real-mode only 386 which can only run DOS. Furthermore, I wonder if there are many games/applications which run in real mode which sense a 386 is present and then take advantage of the 32-bit instructions... If not, then th...

MicroCoreLabs

Also from reading wikipedia, it mentions that 386 embedded chips did not have real mode at all.

Could you please share where you found this?

MicroCoreLabs

Would a 80386 that only operates in real mode be interesting? Implementing protected mode is a heavy lift and DOS doesnt even use it...

Speaking of which, was the 386 widely used as an embedded processor? If so, was it used in real mode or was there a need for protected mode in embedded applications?

MicroCoreLabs

If you only want a speed boost then it can be achieved most easily by making improvements to the PCXT core - I have posted notes in this forum on how it can be done. If there is no interest in this level of effort then developing a new 80286 core and chipset are even more unlikely...

MicroCoreLabs

The MCL86 has become more visible because of the MiSTer PCXT core which I have all of you to thank for!

MicroCoreLabs

As I understand it, this team didn't make the existing 8088 emulator. They took it from another project, struggled with it for awhile, and then MCL86 improved it some. They didn't do a ground-up creation, they took an existing thing, and tweaked it to work better, and even that took a lot of work. This is not true. I am the author of the MCL86 who...

MicroCoreLabs

Interesting tests.. Thanks for running them! The first group which both the MCL86 and 86Box fail are MUL/DIV opcodes which have undefined flags so there is practically no way for us to emulate this behavior. The 0xF7, 0xEB is also an IMUL, so it is probably just random luck that 86Box got it correct. The 0x9F is LAHF and the MCL86 does not copy a '...

MicroCoreLabs

Has anyone tried Area5150 with all of the bug fixes and upgrades recently?

MicroCoreLabs

I can already hear the monotonous Pengo song in my head.

https://www.youtube.com/watch?v=d_aj3bG45ag

Pengo isnt much fun when the 8088 is not cycle accurate.

MicroCoreLabs

spark2k06 wrote: ↑Tue Nov 15, 2022 2:35 pm
kitune-san wrote: ↑Tue Nov 15, 2022 2:31 pm hmm.. I don't know what to say.
I have not found any bottlenecks yet.
However, I would not say that there is not something that is a bottleneck.

MicroCoreLabs wrote:
Let's see what @MicroCoreLabs has to say

But having ao486 already, useful for exactly what

You tell me. You just ran speed tests and asked me what the bottlenecks were...

MicroCoreLabs

for example, how about having an 8087?

Virtually nothing uses the 8087... Maximum speed will always be useful.

MicroCoreLabs

You can add another interface to your BIU which has the full 20-bit address and 16-bits of data (MCL86 EU is 16-bit, just like real 8088) which attaches directly to your DRAM controller block which already has ports for the BIU and DMA. When the CPU attempts an access to DRAM which you want to accelerate the access happens over this new BIU port. Y...

MicroCoreLabs

They are very interesting, but would be difficult to incorporate into the same core as the current stable 4.77 MHz system. Great achievements are often difficult... You can use my MCL86jr BIU as an example which accesses an external SSRAM at both 4.77Mhz cycle accurate and fastest possible speeds. https://github.com/MicroCoreLabs/Projects/blob/mas...

MicroCoreLabs

Let's see what @MicroCoreLabs has to say :-). You can try: - Running the microsequencer faster than 100Mhz. The FPGA can probably synthesize to a much faster clock speed. - For SDRAM accesses you can bypass the BIU state machine and complete cycles in the minimal time. This would yield the best results. - Mirroring the BIOS ROMs in FPGA RAM and ac...

MicroCoreLabs

None of that's easy, but it seems a lot easier than an 80386-from-scratch would be. It would probably even be easier than a 286-from-scratch. But that's a guess based on zero FPGA programming experience. Developing CPU cores is time consuming and difficult.. at least it is for me.. :) Some of the recent bug fixes for the MCL86 were absolute needle...

MicroCoreLabs

Even less than 25MHz could be the maximum limit imposed by the MCL86 architecture, if I'm not mistaken... I think @MicroCoreLabs said something about that.

Did I say that?

I covered this in a previous post, but you can achieve the greatest acceleration by changing the BIU to complete DRAM accesses outside of the local bus state machine.

MicroCoreLabs

The MCL86 does work in a real PCjr

https://www.youtube.com/watch?v=BUYmz3fqxss

MicroCoreLabs

For the PCjr experiment is there any way to insert a CTL-ALT-INS which, after the splash screen, begins the internal diagnostics. It will display a menu and memory count at the top the screen which would be interesting to see.

MicroCoreLabs

The updated microcode has been uploaded to my GitHub repository. Please let me know how it works!

MicroCoreLabs

I now see that the CF/OV flags are used by iDIV and DIV so need to be cleared. IMUL and MUL clears these flags in the microcode so no changes are needed. I will update the microcode ASAP. IDIV is easy because the first microcode instruction is currently a NOP which can easily be changed to the CF/OV clear instruction. DIV will be a bit harder are t...

MicroCoreLabs

Yes, it looks like changing that line of microcode to a NOP is the best fix. I verified that each 0xF6 opcode sets the Carry and Overflow flags independently so there is no need to pre-zero them when the 0xF6 opcode is recognized. The mistake was when a microcode operation is shared between opcodes I tried to perform it just once to save the microc...

MicroCoreLabs

Yes, the NOT opcode should not affect any flags, but I am clearing them in the common 0xF6 code. Your NOP fix may be the best fix, but let me investigate to make sure this solution will not affect other 0xF6 opcodes. Thanks!

MicroCoreLabs

When a word access is executed to an I/O device (out, in), is the address incremented on the second access?

Yes it does increment. Please see my BIU code on GitHub. Also remember that the address will wrap over the segment.

For example a word read at 0xAFFFF will read from 0xAFFFF and then 0xA0000. It will not read from 0xAFFFF and 0xB0000.

MicroCoreLabs

It would be very hard to emulate this behavior exactly so I just picked a number in the middle of the range which yielded good results.

This was my full statement.

Practically anything can be done in a software emulator so there is no surprise that cycle-exact emulators exist. Doing so in microcode running in an FPGA is a different story...

MicroCoreLabs

The MCL86 is cycle accurate, but not cycle exact. I'm not sure anyone has achieved this yet in hardware but I believe the MCL86 comes the closest. For opcodes which complete in a range of clock cycles like MUL and DIV the MCL86 will use a number in the middle of the range. The real 8086 uses a combination of microcode and hardware for multiply and ...

MicroCoreLabs

These are all good points but I will leave it as a project for someone else.

MicroCoreLabs

It looks like PCXT passed all that tests :), this is how it looks like after running "runall.bat": Yes, this was the desired result! :) I wrote all of these tests on a genuine IBM PCXT using QEdit and then ran them on a PC which had an MCL86 installed. For opcodes which failed I single-stepped the same test on both computers using D86 to...

MicroCoreLabs

Here are the tests I wrote to verify the MCL86 core which touch on the opcodes, addressing modes, and flags. https://github.com/MicroCoreLabs/Projects/tree/master/MCL86/Tests It compiles using A86 into .COM files which run under DOS. I'm sure they are not 100% exhaustive but were good enough to verify the core to a large degree. Source code is simp...

MicroCoreLabs

Maybe you can try using distributed/LUT RAM for the 16KB of MCL86 microsequencer ROM instead of block RAM since you seem to have lots of spare LUTs?

MiSTer FPGA Forum

Search found 96 matches

Re: Instruction prefetch cache?

Re: Ideas for PCAT

Re: Ideas for PCAT

Re: Ideas for PCAT

Re: Ideas for PCAT

Re: MCL86 featured on hackaday

Re: Tandy 1000 TX?

Re: Some 8088 instruction bugs

Re: Interesting Tests We Could Run For x86

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: PCXT Core 10Mhz CPU Speed Possible?

Re: IBM PCjr BIOS in PCXT Core

Re: IBM PCjr BIOS in PCXT Core

Re: FDD Support Based on ao486 Implementation

Re: FDD Support Based on ao486 Implementation

Re: Some Research Over the Keyboard Issues on Hang Shift for Keyb sp

Re: Some Research Over the Keyboard Issues on Hang Shift for Keyb sp

Re: 8088 CPU

Re: 8088 CPU

Re: 8088 CPU

Re: Interesting Tests We Could Run For x86

Re: Interesting Tests We Could Run For x86

Re: Interesting Tests We Could Run For x86

Re: Saving BRAM To Facilitate Ports and New Developments