MiSTer FPGA Forum

Does anyone know the exact latency requirements for SRAM? I can't find it anywhere, only that it's less latency than the DDR3. The Alliance SRAM used on the 128MiB board has 3 cycle CAS at 143MHz, about 21ns; that doesn't account for row precharge, row-to-column, etc.. It's also $13 per chip, and you need 2. New HyperRAM at 250MHz has 28ns initial ...