MiSTer FPGA Forum

Hehe - thanks - it was a bit of a killer to finish this one. Unfortunately it just gets more and more complicated!! Still, all good fun.

Displaying a tilemap tank graphic on the screen using logic chips and the Tank Battalion character rom chip, then explaining how it works (hopefully..)

This time it's all breadboard, but next time the Verilog code is done so the same thing can be shown from the MiSTer.

So I was hoping the actual hardcopy book had better diagrams than the hand drawn ones. I was so relieved to see that they are! On the logic analyzer ideally there'd be one that does 24 channels, because you'll see later in the videos that we need to see the address lines and the data lines at the same time. I'll use the Ben Eater method of using an...

So I bought the Andre LaMouthe book and also the course on Udemy was only $11 - it's hours and hours long, so I say it's a steal. Overall some really excellent info there. Thanks for putting me on to the book and the course.

Displaying a color pattern on the screen using logic chips and then implementing the same design in Verilog on the MiSTer platform.

MysteryM10 - thanks. Yes - we'll have Episode 4 coming in the next day or two - it's getting a video picture on the screen.

Completing the timing circuit & TV sync signals of the Namco Tank Battalion arcade game, on both breadboard and in Verilog & Modelsim software.

Yes - it's from the TTL book from Texas Instruments. You can get it from this link: https://www.ti.com/lit/ug/scyd013b/scyd013b.pdf Just a quick point - the TI book has the pinout and logic 'truth table' on different pages - by the magic of video they are together, so don't go looking for a page with both on, because you won't find it! Most other d...

Mine was that and an Akai Sampler S3000, with the CD-Rom. I actually got an Akai S612 that had the same disks as the Amstrad 6128 - the 3" jobs!

It's funny - I was heavily into synths and samplers after my 8-bit computer days, probably the reason I never got into the 16-bit computers. I haven't looked much into the sound side of FPGAs, but I can see that becoming a real rabbit hole!

Thanks for the feedback!

I've just bought that book too, since it looks really really good. Can't wait to get it.

Great website too. Thanks.

Alkadian,

This book looks amazing. Thanks for the link - I had no idea this existed!!
You probably know about my video series on MiSTer core development. But if you don't, check out episode 1 that has a resources section. A good book in there about arcade design - it is a bit old though.

https://youtu.be/qxgM9NPrhqw

Xbytez - I'm honored that you'd be posting my videos to this site. Thank you!! I was going to do it myself by I see you've been me to it. If there are any questions about the content please fire away. The EP2 was actually getting to be close to an hour so I've split it into 2 parts. The now EP3 will be coming out pretty soon too, since it's almost ...

I'll give it a go. I didn't now you could have it ready for acquisition if you didn't use the Program Device route!
Thanks.

I'm going to do an upcoming video about how to get over this with the 6502 core.

Thanks - I'll setup the code in a github. At the moment I'm just fudging the MiSTer shell to allow the pass-through of the comp sync and RGB signals, so it's only working on my CRT. The strange thing is that if I change the order of the up and right control inputs it works. I really don't see how that would affect anything. I can use Signal Tap to ...

Hi, I wonder if anyone has had a similar issue. I've put together a simple arcade core - I'm going to start publishing the step in videos coming up - anyway I'm putting the controller inputs into my core as so (Verilog): .BUTTONS(~{m_coin, m_start, m_bomb, m_fire, m_right, m_left, m_down, m_up}), This is the standard setup for the controls as far a...

The answer by the way, is no, it's not.

Is it possible to use the low PHI clock cycle for RAM access with the Arlet 6502 core - as in a real 6502 chip? Most cores (maybe all) I have seen just split the VRAM circuitry from the operation of the 6502 core, but I'd be interested to know if you can indeed mimic actual hardware ram/rom timing or it's not actually possible.

Thanks,
Nick

Great news in the works it sounds then!

Interesting that FGPA Arcade already has some of these Konami titles - shame it's not open like MiSTer. Oh well, in time we'll have them.

Thanks - but can't see the EDIT key on there.

Anybody know how to get the special keys to work - like EDIT or Graph key etc.?

Thanks Paul.

I put together an actual 65C02 chip with 32kb of Ram and 32kb of Rom. In the ROM I placed a few bytes of test code: At FFFC 00, FFFD 80 - the reset vector to point to address 8000 to start the code I won't bore with the code but essentially load 42 into the accumulator, and then load address 2000 and write the number 42 to address 2000. It then doe...

Turns out IT'S IN THE PAC MAN MANUAL!!!!!

Very happy to see that indeeeeeed!!!

Does anyone know if the custom chips have available schematics anywhere on the internet? There are two custom chips: VRAM Addresser Sync Controller They have daughterboard equivalents with, I think typical TTL chips. However can't find any info. I know it is possible to just bypass all those chips, if you re-write the code in a non-schematic way. I...

So I worked out if you type MTXL and then switch the display mode, you are in basic.

Is it possible to get into BASIC? Any ideas how this might be done?

Thanks!

This is some of the most clearly written code I've seen for an arcade core. I will really be able to understand what is going on, for a change. Thanks.

The FPGAarcade - Replay board etc. team seem to have some 6809 cores released, such as Yie Ar Kung Fu & Hyper Olympics.

Interesting development - but seems to be very much NOT open source. Is there any more information around on such cores?