MiSTer FPGA Forum

This issue seems to occur when a soft reset performs a reset operation on an interrupt or timer module.
Perhaps the soft reset implementation of the chip(8259 or 8253) is inappropriate.
I will investigate this when I have time.

My SDRAM(KFSDRAM) module was not intended for use as video RAM or dual port RAM.
It really only provides simple functions. Burst mode and multi-bank are not supported.
Perhaps it would be better to create a new RAM module.
Or, if there is an existing high-speed SDRAM module, it is better to use it.

MiSTerPCXT used a specific table for geometry calculation(storage CHS).
However OS seems to have already booted, so it may not be related to this issue.

https://github.com/MiSTer-devel/Main_Mi ... p#L54-L198

Thanks.

To confirm that the BIOS is really writing H=2, could you please try the following conditions to see if it triggers

cpu_address=306h
data_bus=02h or X2h
io_write_n=0h
ide_cs1_fx=0h

The fix suggested by slingshot2 in the atari forum may solve the problem

It really does have H=2...
we need to look into what is writing this.(bios or mist system)

In Mister, the boot sector readings(Read sector command (C4)) are as follows:

C = cylinder[15:0]=0
H = drv_addr[4:0]=0
S = sector[7:0]=1
As expected, CHS=0/0/1.

I am now trying to get waveforms under the same conditions with MiSTer, but it may be difficult to get waveforms with MIST where the registers are not visible.

Well, I am not the author of universalbios, so I can't say for sure, but I believe that if the BIOS is working right, it will read the boot sector first.
I suspect that the correct values are not being written to each register (drive, sector number, sector count, cylinder).
I am going to add each register to Signaltap.

somhi wrote: ↑Mon Mar 06, 2023 9:02 am

Don't know why you can't see the image. Try open image in a new tab. The image shows the trigger at the conditions you said so that is working.
have a look at https://atari-forum.com/viewtopic.php?p=444047#p444047 if you can see images also

I don't know why. It looks to me as follows. Do I need to register as a user?

Lately I have not been improving my MMC module.
I will restart that soon.

I'm not familiar with ISE, so I could be wrong...

it probably affects both.
The reason the result is "All constrains met" before my constraints are added is because it is unconstrained.
Since they are unconstrained, they can be freely placed and are not analyzed.

I can't see the image for some reason. (Permissions?
I think bios reads the first sector first.
We need to make sure the correct values are written to each register(drive, sector number, sector count, cylinder).

I installed ISE, but I don't know how to do timing analysis...

oh. I've been using SystemVerilog so much that I've forgotten the Verirlog specs...
The previous commit is revert.

Are you using the same XTIDEBIOS as MiSTer?
BIOS ROMs created in the early stages of MiSTerPCXT development may not work properly because the settings do not match.

I fixed the wrong declaration of signals that occurred during conversion.
Please give it a try when you have time.

https://github.com/kitune-san/PCXT_ZXUn ... ab74e5b6bc

When I used ZXUno files in MiSTer, the MMC module behaved strangely.
It appears that there are some incorrect conversions of reg and wire.
This will be corrected manually, so it will take some time.
Also, there was one undeclared signal that I will fix as well.

There may be a timing-related problem inside the FPGA, or there may be a problem with the verilog conversion.

First, I will replace the mister's mmc module with the one used in zxuno.
I will try this when I have time.

I see that the core is not reading the status register.
The read pulses need to be corrected and the IDE module needs to be scrutinized.

If you have time,
Could you connect the control_state signal of KFMMC_Controller.sv to the test port?
By looking at this signal, you may be able to tell which process is failing.

If this pin is floating, power may not be supplied to the card.