MiSTer FPGA Forum

@Alkadian,
Thanks!! At the beginning of the week I was getting way more subscribers than typical, so I thought something was up. I did a search and found that Hackaday article. Great to have the coverage! We're close to getting a working core, just minus the sound for now. So that's going to be fun trying to implement that.

Don't tell anyone, but the secret is that I didn't start making the videos until I knew it worked!!

Looking at how RAM, ROM and peripherals are addressed by the 6502 in our core and then review of the Verilog for the MiSTer. Finally we launch the actual core for the first time.

Thanks MISTerMark - that's a really great resource.

Looking at how contested VRAM access is handled between display and CPU circuitry in hardware and then in Verilog for the MiSTer. I put the logic analyzer on the circuit to see what's going on.

Just as easy to take the verilog code and just connect it up like that. Not visual, but practically the same.

That's awesome. I shall be 'borrowing' that code!

One thing I would say, my problem was, looking a bit and then trying to look at something else, or thinking some different hardware would allow me to 'get it'. In the end the only thing that let me get it was building it on a breadboard first and then doing it in Verilog. That's why I'm trying to shorten that learning curve in my videos. I think yo...

Rog my first video has a bunch of resources including books. I would definitely persevere with the 8bitworkshop book because, as you say, it is tailored specifically for video games. I go back to it all the time!

One point with the book cited is that, as you mentioned, it is designed to be used with the online IDE. It's a bit quirky compared to writing for an actual FPGA. Still very useful though. He makes some leaps that I personally found a little difficult to understand. Of course, I would shamelessly plug the MiSTer Retro Wolf channel on Youtube, since ...

Ok- so was looking around the menus. There is something called GLOBAL Volume (rather than Core Volume) that was set to MUTE by default. That's what it was. In case someone has the same issue!

Thanks bbond007 for the suggestions. Yes plugged in, both tried the HDMI output and the IO board sound out. Both global and game setting changed about to test for a few different games. MiSTer updated constantly. Oh well, I guess it's one of those ones I won't solve. Thanks.

Any sound on any game.

Any ideas why my sound may not be coming through?

Needed to create a fresh system SD card, so started out fresh with SCUMMVM. Now I have no sound at all, apart from that all running ok. Any ideas why I wouldn't be getting sound? thanks.

It would be very good to have this IIGS core! I've always wanted to get a system, it was just a little too out of the price range. Would be excellent to play around with this, so really good news it's in development.

That's funny. Cheating in the sense of not doing all the background research into the system yourself, so cheating the 'system'...

Ha! Thanks. Yes I can see it's going to really make a difference with checking out arcade boards.

A continued look at how to implement a 6502 CPU with RAM and ROM in hardware and Verilog for use in MiSTer cores. The hardware test circuit is analyzed and simulated in Modelsim, with discussion.

So great to see this core!! Very happy about it.

A look at how to implement a 6502 CPU in Verilog for use in MiSTer cores. The hardware test circuit from the last episode is simulated in Modelsim, with discussion.

Looking into the 6502 chip, it's history and how it works, with a small test circuit and code review.

Slypty - the core that I'm developing - but I'd say many of the arcade cores are outputting a composite sync on the HSync input. That is, the VSync and HSyncs are superimposed on that input. The VSync is not needed under this configuration. Now I am using a PVM and this may make it a little more flexible in terms of what it accepts for sync but I'm...

Hi thorr - the tutorial series is building from the ground up. You could say that, currently, up to now we're only really using the DE10-nano with the added IO board. I'm not using any of the MiSTer framework that supports the HDMI, VGA port, USB etc. The reason is, if I included the framework it would be REALLY complicated and I want it to be as s...

All episode have been updated to now include optional code for VGA output rather than CRT output. Useful for anyone wanting to follow along without a CRT.

Displaying a test pattern on the screen from a Rom chip using the Tank Battalion character set, this time in Verilog.

A simple one this time. Next time we'll be diving into the 6502 CPU actual hardware and then how we implement it in Verilog.

MiSTer Core Dev Episode 7: Test Screen Rom

Displaying a test pattern on the screen from a Rom chip using the Tank Battalion character set.

MiSTer Core Dev Episode 6: Verilog Rom Chips

Displaying tilemap graphics on the screen using a Verilog implementation of the Tank Battalion character rom chip, then explaining how it works (hopefully..)

Ah = yes, I use FeeUEF to play them through the audio cable. There was a site where someone had analyzed the format of UEF files, but it's a bit of a headache!

What part of the Electron tape wasn't working? The last core had it working just fine.