Sorgelig wrote: ↑Sun Jun 07, 2020 12:00 pm
Where i can read technical info about Next video modes? I need to know which video modes are supported and where video frame buffers can be.
You have a lot of information in the ZX Spectrum Next Wiki.
Here
https://wiki.specnext.dev/Memory_map you have the map memory
The layer2 and shadow layer2 spend continuous 3 banks of 16KB each (in total 6 continuous banks ) . But the position is variable.
NextZXOS moves the Layer 2 bank assignments. Therefore, Layer 2, after NextZXOS boots, is mapped to 16k-banks 9-11. The Layer 2 shadow memory is also assigned to 16k-banks 9-11.
layer2_active_bank -> std_logic_vector(6 downto 0) is the starting 16K bank
The default value of
layer2_active_bank is 8 --> "0001000" (minimum value) and the maximum value of this variable is 106 --> "1101010"
The default value of
layer2_shadow_bank is 11 --> "0001011"
Be carefull although the bank number of default layer2 is 8, it start after the bank 0 start in $040000 so we have to add that ofsset.
it is shown in this line (we add +1 to add the offset of $40000) -->
Code: Select all
layer2_bank_eff <= (('0' & layer2_active_bank_q(6 downto 4)) + 1) & layer2_active_bank_q(3 downto 0);
layer2_bank_eff is the bank effective abd it is used to calculate the absolute address layer2_addr_eff
Code: Select all
layer2_addr_eff <= (layer2_bank_eff + ("00000" & layer2_addr(16 downto 14))) & layer2_addr(13 downto 0);
So theoretically we have to create a VRAM containing the 6 blocks X 16 Kb of Layer2 banks and Layer2 Shadow banks.
My actual core is running in a Cyclone V 22K cells using SRAM
So, I gonna use the same SDRAM instanciate of your Spectrum core but I have to solve the logical part of the VRAM with variable address.
For me the VRAM will have 96Kb and
1) I will read in it when the core accesses to port B(layer2), but I have to send to the VRAM memory the relative address memory of the layer2 (my starting reference address is always 0) instead the absolute value of the complete address total RAM.
2) To read/write in CPU the core uses port A. The data will be send to the SDRAM unless the part A writes in VRAM (see the next case)
3) To write in VRAM (the core uses the port A), I have to use logic to know if the memory address to write belongs to the VRAM (layer2 or layer2 shadow bloks) or is the rest of the complete RAM. If it belongs to VRAM , I have to convert the absolute address in relative to VRAM and write in VRAM and SDRAM at the same time. If the memory address belongs to the rest of the RAM memory I have to write only the absolute address in the SDRAM only.
Do you think I am right?
Solving this part I think I have the core done, I am really close, maybe I am gonna need your help in the this part.
Thanks