IEC example circuit please

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yellperil
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IEC example circuit please

Unread post by yellperil »

Has anyone implemented/tested the new IEC interface out to real hardware yet?

I'm a bit confused as to how it would work?

I've built one in my custom c64 core using separate Data (in/out) and Clock (in/out) lines like this https://ist.uwaterloo.ca/~schepers/MJK/serialbus.html

But I don't know how to do it with the lines already combined. Is it simply just whack a logic level converter in and that's it?
I'm assuming it is reliant on the version of the I/O board with pull ups on it.
jalbarracin
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Re: IEC example circuit please

Unread post by jalbarracin »

What I understand is that original C64 pins are 5V and MiSTEr works with 3.3V
Hope somebody can clarify this.
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yellperil
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Re: IEC example circuit please

Unread post by yellperil »

I've had a go at the circuit but the looking at signals coming out of the FPGA they are at all LOW with no activity on the bus,
They need to be inverted to HIGH so they can be pulled down. ie HIGH being 0 and LOW being 1.

Is there some trickery in the FPGA to be able to Invert them like the 7406?

EDIT : Actually the signals are high, but when I access the external drive they all get pulled low and stay low until the drive is reset.
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aberu
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Re: IEC example circuit please

Unread post by aberu »

yellperil wrote: Thu Jun 10, 2021 7:55 am I've had a go at the circuit but the looking at signals coming out of the FPGA they are at all LOW with no activity on the bus,
They need to be inverted to HIGH so they can be pulled down. ie HIGH being 0 and LOW being 1.

Is there some trickery in the FPGA to be able to Invert them like the 7406?
It depends upon if that pin as assigned to the FPGA is compatible with "inout" (verilog/systemverilog) or capable of being an input and/or output. You can also set any of these pins to either in our out. The problem is, if the pins you are using are assigned to the user IO port and they are static in the framework, you may need to adjust the framework side of things in "/sys/" for the template to do this. Your results my vary, proceed carefully.

https://github.com/MiSTer-devel/Templat ... op.v#L1410

I believe this is one of the relevant sections.

I'm not a dev though, so hopefully someone else can weight in and elaborate.
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