32-bit cores

xohs
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Re: 32-bit cores

Unread post by xohs »

I have an archive of most versions of SunOS, Solaris, NeXTStep, and OpenStep if you need them for testing.
xolod79
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Re: 32-bit cores

Unread post by xolod79 »

Sorgelig wrote: Fri Jul 03, 2020 10:52 pm
xolod79 wrote: Fri Jul 03, 2020 10:32 pm
And all 680x0 core dosen't have MMU. that does not run unix on them!
MMU present since 68030 (not EC or LC).
I wanted to say that. I am not aware of more than one open source MMU implementation for 680x0.

There is also an interesting proposal to implement a virtual ethernet adapter using a TAP device. what will require adding to the Mister framework a service for transferring ethernet packets between fpga and HPS (probably through shared memory?). just like it was done with sound cards. This solution will allow it to be used for other cores Minimig, Ao486 and others. I know that this is obvious to many, do not scold me.
rolopolo
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Re: 32-bit cores

Unread post by rolopolo »

I do have a spare station 10 which I think I a had dd image of running Nextstep. Dunno if that would help anyone. The Risc NS OS install images about are all DD images, no passwords on those. The SS10 is not a NS machine at the mo as it has an unsupported processor card inside right now.
bigvalen
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Re: 32-bit cores

Unread post by bigvalen »

I giggled like a child, when I brought up SunView....brought back old memories.

How hard would it be, to get networking going ? Is this a problem that'd impact most projects ?
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Grabulosaure
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Re: 32-bit cores

Unread post by Grabulosaure »

@bigvalen

Some cores support networking though serial port (PPP...) : Amiga, AO486. The SparcStation core also has an internal serial port accessible from Linux side, it can be used for the console and hardware debugger ("debug" ARM executable), it could be used for networking.

Networking worked on the old Xilinx dev board with had an MII PHY. A RMII PHY requires 7-8 signal pins.
cb88
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Re: 32-bit cores

Unread post by cb88 »

So here's a thought... Sparcstations could have up to 512MB ram on the SS20 (or 7x64MB + 8MB VSIMM to enable onboard graphics), there was also an nvsimm slot which could take another ram card out of the picture to provide nonvolatile memory to accelerate NFS etc... , (1GB on the Hyperstation 30), I was reading that nobody had an excuse for more than 128MB on a mister... well how about now! If two ram boards were used, that would double the available bandwidth also. I also wonder if with some concessions you could get 256MB on each board, I doubt the SS core, needs the ram to run at maximum clocks. A sparcstation 20 can *definitely* use that much ram... when heavily loaded with compiling stuff.

I like the idea of implementing a standarized ethernet card, with software support on the ARM CPU side since then any Linux supported network adapter can be used. But just wring up a Microchip ethernet chip is generic across what temlib supports outside of Mister.
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Re: 32-bit cores

Unread post by pacoarcade »

OpenBSD/sparc could be a nice candidate for testing the core. The last release supporting this architecture is 5.9 (ftp).
cb88
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Re: 32-bit cores

Unread post by cb88 »

OpenBSD as you mention is no longer updated, even though I found it a bit more ergonomic. NetBSD, acutally gets updates on sparc, and has better hardware support in general, so as hardware is added to the sparcstation FPGA image, NetBSD is your best bet. You can use the pkgin package manager to get a better experience than attempting to build software yourself.

Also sadly Linux dropped support for 32bit sparc the other day ... perhaps it can be revived but for the time being that is dead. If anyone wants to contribute to get Linux support back going I suppose you could try but I don't think it would be super welcome I think they are tired of supporting it, of course it could be support outside of mainline not much of a big deal.
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Grabulosaure
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Re: 32-bit cores

Unread post by Grabulosaure »

cb88 wrote: Sat Dec 19, 2020 6:41 am So here's a thought... Sparcstations could have up to 512MB ram on the SS20 (or 7x64MB + 8MB VSIMM to enable onboard graphics), there was also an nvsimm slot which could take another ram card out of the picture to provide nonvolatile memory to accelerate NFS etc... , (1GB on the Hyperstation 30), I was reading that nobody had an excuse for more than 128MB on a mister... well how about now! If two ram boards were used, that would double the available bandwidth also. I also wonder if with some concessions you could get 256MB on each board, I doubt the SS core, needs the ram to run at maximum clocks. A sparcstation 20 can *definitely* use that much ram... when heavily loaded with compiling stuff.

I like the idea of implementing a standarized ethernet card, with software support on the ARM CPU side since then any Linux supported network adapter can be used. But just wring up a Microchip ethernet chip is generic across what temlib supports outside of Mister.
The DE10nano has 1GB of DDR3.
512MB is used by the ARM core and Linux, 24MB is used by the scaler, a few MB is used by audio buffers.

So the rest can be used by the cores : The SS20 uses 484MB for RAM and a few extra megabytes for video framebuffer and boot ROM.
It could be possible to get a few extra MB from DDR3 and use the SDRAM daughterboard (but it has lower bandwidth than DDR3).
But 484MB is already far, far better than the 128MB available on the old Xilinx SP605.

Ethernet is really needed for a full SparcStation "experience".
cb88
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Re: 32-bit cores

Unread post by cb88 »

Yes I know but the SDRAM has lower latency than the ARM memory which has to make a few more hops...still it may not matter too much if there is at least some cache implemented in the core.

Yes the mister board is quite good, I just ordered one. My only point about the ethernet was, if the mister side of things implements a fake ethernet in software, with a hardware interface exposed to the core it may be quite nice to use that since you could keep the networking wireless.
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Re: 32-bit cores

Unread post by xolod79 »

@Grabulosaure
Hello!
Have news about your SPARC core?
Fluff
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Re: 32-bit cores

Unread post by Fluff »

Hi, I’m new to MiSTer, but I’ve used SPARCstations and NeXTSTEP a lot back in the ‘90s, so I’m very keen to try this core.

I’ve grabbed all the files from the FTP site and successfully unpacked the OS images for SunOS, Solaris and NeXTSTEP, but when I boot the SS core, it cannot find any of the OS images or the raw.img. Where should I put the files on the SD card for this to work, please? Do I need to put anything in the secondary SD card or all on the primary SD?

So far; I can see the core in the MiSTer menu and boot it and I see a black screen. If I bring up the OSD menu and try to load an img or a rom file, it doesn’t find anything. I can’t reach the white OpenFirmware screen with the boot prompt.

Thanks
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Re: 32-bit cores

Unread post by jca »

They should go in games/SparcStation. I did not play with this core in a very long time but I have never been able to fully boot NextStep. I also had problem shutting the others properly, likely due to my lack of knowledge on these 2 OS. I regularly destroyed the Solaris hard disk, lucky me it is only a virtual one.
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Re: 32-bit cores

Unread post by jca »

I just tried, the OpenBIOS screen comes up, I can select the raw file but I cannot remember how to boot:
boot -> Trying disk...
No valid state has been set by load or init-program

I remember I had to type something else but cannot remember.
At least the name of the directory is correct.
Fluff
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Re: 32-bit cores

Unread post by Fluff »

Thank you, I've got it working now, this is very impressive. SunOS worked great, but NEXTSTEP is flaky. By default, it's detecting 256 MB RAM and that can cause instability, so I've booted up with the "-v config=Default maxmem=65536" kernel flags and managed to log in to the desktop, but it's crashing and logging me out and repeats in a loop. Still, very promising so far. Thank you to Grabulosaure for creating this.
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Re: 32-bit cores

Unread post by jca »

How do you boot them? I used to be able but now I get stuck in the OpenBios.
Fluff
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Re: 32-bit cores

Unread post by Fluff »

I load the core, then bring up the OSD menu, choose the 'mount image' option, select OS image, use the 'reset' option in the OSD menu and wait. It takes a long time, but eventually the OpenFirmware boot prompt appears, then I type 'boot' and wait for the OS to boot.
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Re: 32-bit cores

Unread post by jca »

It is what I used to do a long time ago but now it does not work any longer on my setup. I have to investigate and I suspect it has something to do to the fact I have everything on a USB drive. This weekend I will make a SD card where I will run it from the SD card, no USB drive and see what it gives. Thanks for confirming.
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Re: 32-bit cores

Unread post by throAU »

antonie wrote: Thu Jun 18, 2020 10:29 am Hi all,

Is it feasible to implement 32-bit cores in MiSTer?

I was looking for a way to get NextStep on to MiSTER and came across this project:

http://temlib.org/

It's basically an implementation of sparc32 in fpga.

From the website:

"There is also an unfinished version (complete but with bugs) for an Altera CycloneV GX (Terasic “Cyclone V GX Starter Kit”)

+——————————————————————————+
; Fitter Summary ;
+——————————————————————————+
; Device ; 5CGXFC5C6F27C7 ;
; Logic utilization (in ALMs) ; 9,490 / 29,080 ( 33 % ) ;
; Total registers ; 11070 ;
; Total pins ; 324 / 364 ( 89 % ) ;
; Total block memory bits ; 560,896 / 4,567,040 ( 12 % ) ;
; Total RAM Blocks ; 83 / 446 ( 19 % ) ;
; Total DSP Blocks ; 5 / 150 ( 3 % ) ;
; Total PLLs ; 1 / 12 ( 8 % ) ;
; Total DLLs ; 1 / 4 ( 25 % ) ;
+———————————+——————————————–+"

http://temlib.org/site/?p=567

There are already plenty of 32 bit cores:
  • Minimig
  • Atari ST
  • ao486
  • Archimedes
  • NeoGeo
etc.


That said, the NEXT computers were 68k based, not Sparc. You could run NextStep on Sparc, but the native platform was 68k based (with some additional hardware).
Fluff
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Re: 32-bit cores

Unread post by Fluff »

Yes, original NeXT hardware used Motorola 68030 and 040 processors, both 32-bit chips. There was also a 32-bit Motorola 56001 DSP coprocessor. The OS was then ported by NeXT to Intel x86 (486DX minimum required), Sun SPARC and HP-PA RISC architectures, targeting their 32-bit chips only. NEXTSTEP and OPENSTEP always required 32-bit CPUs and never supported 64-bit CPUs (until the Apple merger when Mac OS X evolved, but that’s another story).

We would need at least a 68030 + 68882 + 56001 DSP core to implement NeXT hardware, which may not be feasible given DE-10 Nano’s current capabilities.

NEXTSTEP is booting on the SPARC core right now and I can log into the desktop, but it seems unstable and I always get logged out when some critical system process crashes (Workspace Manager or the loginwindow). Still, a very promising start and super impressive considering this is an early beta core.
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ron
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Re: 32-bit cores

Unread post by ron »

Looking through the Git I found a core of HP9000/300 and casually I realized that it mounts a 030 ...
https://github.com/svenschnelle/hp300_MiSTer

I dive a little and find the origin of the 030:
https://github.com/AmicableComputers/wf68k30L

Are we facing a possible and viable 030 core in FPGA?

regards
xolod79
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Re: 32-bit cores

Unread post by xolod79 »

Compiled by RBF https://github.com/xolod79/hp300_MiSTer ... 210802.rbf.
It starts up, but doesn't figure out how to start BASIC from ROM. Maybe someone knows?
In general, the project is very interesting! I wanted the author to continue to develop it. I think the main problem is the lack of an MMU for the 68030.
sjuswede
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Re: 32-bit cores

Unread post by sjuswede »

Is the temlib project alive at all? Is there anything we can do to help? This is a really cool project, and I for one really love it.
xohs
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Re: 32-bit cores

Unread post by xohs »

Question about the SPARC core if you are still around @Grabulosaure.

There are two versions of SS.rbf on your site -

First one, dated 2019-12-03, ~4MB in size, located here:
https://temlib.org/pub/mister/SS.rbf

Second one, dated 2019-11-1, ~3MB in size, located here in the "SS" subdir:
https://temlib.org/pub/mister/SS/SS.rbf

I'm assuming the best one to use at the moment is the 4MB core with the later timestamp? Are there any newer builds that might be better to test with? Thanks!
xohs
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Re: 32-bit cores

Unread post by xohs »

I was able to get the SPARC core working. Here's a bit of a dump on the process. All paths below are on the sd card (mounted at /media/fat). I use the update_all script normally so that's how my directories are structured.

_Computer/SPARCstation_20191203.rbf (downloaded and renamed this core.)
BIOS/SPARCstation/boot1.rom (this is the boot.rom file from temlib, I had to rename it to boot1.rom for whatever reason as it would not see the boot.rom file.)
SPARCstation/sunos.raw (from the temlib site, unzipped and extracted.)

I loaded the SPARCstation core from the initial MiSTer menu, hit F2, mounted the .raw partition, and loaded the .rom file. Black screen will sit there for at least ~2-3 minutes before the familiar white SunOS boot screen comes up. I did not have to change anything to boot SunOS 4.1.4, it just loaded straight-away. Root has no password and the readme file suggests running /usr/openwin/bin/openwin to start the GUI. It comes up pretty quickly.

I noticed that it shows an ethernet card, le0. I'm not sure what that is about as the earlier threads seemed to indicate that it was serial-only. If any of you are aware of the status of the network card I'd appreciate a reply.

More to come as I test out Solaris and NeXTstep.

Fun sidenote to follow-up with - I just successfully booted NetBSD/sparc 9.2 on this core. Haven't tried XWindows with it but the actual OS booted up with no errors. I installed it via QEMU/sparc on my PC, converted the disk from qcow2 to raw, moved it to the MiSTER, and boom it just worked (but sloooowly.)
cb88
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Re: 32-bit cores

Unread post by cb88 »

xohs wrote: Mon Mar 28, 2022 5:09 am
I noticed that it shows an ethernet card, le0. I'm not sure what that is about as the earlier threads seemed to indicate that it was serial-only. If any of you are aware of the status of the network card I'd appreciate a reply.
Note that just because the hardware is in the FPGA doesn't mean its wired to anything..... on the other board uses for TEMLIB you have to wire up an external ethernet PHY for that to actually work if I remember correctly.
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