Learning path for FPGA

Discussion of developmental aspects of the MiSTer Project.
Bas
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Learning path for FPGA

Unread post by Bas »

Hey all. I've been thoroughly loving my MiSTer setup for months now but would like to be able to dabble with it some more. I'm coming more from a home computer conservation angle than a gamer. As such a core that faithfully implements an IBM XT would interest me, even though AO486 is probably already mostly compatible. My feeling is that much of what is needed for such derived cores (for lack of a better word) is already mostly available, it just needs effort to bring together. I'd like to try and see what I'd be capable of myself, cobbling parts together.

My big problem is that I'm a software dev (started in the 80's on 6502 ASM) and am having trouble finding a good place to pick up the learning path towards hardware and FPGA.

I know this is a specialism all its own and I won't be productive anytime soon. Any help in where to start would be much appreciated. Stuff like books or an outline of the curriculum you pro FPGA gurus used to follow in university (I presume) would help.
robinsonb5
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Re: Learning path for FPGA

Unread post by robinsonb5 »

I think I'd start with something simple - maybe take the MemTest core, learn to built it in Quartus, then figure out how to change the background colour and text colour. (My first project was on the Turbo Chameleon 64 cartridge - I took the hardware diagnostic core and used the graphics primitives and PS/2 mouse component to implement a simple "Pong" game.)

You're going to encounter both VHDL and Verilog - both languages have their pros and cons. VHDL will throw a compilation error for the tiniest of mistakes. Verilog will quite often march straight past the most blatantly wrong code and silently produce a non-working core as a result! For this reason, I tend to consider VHDL the better language for learning, at least until you have the base concepts secure.

The most important thing is to understand what type of logic is being described by your code, understand the difference between combinational logic and registers, and understand the difference between blocking and non-blocking assignments.

Would there be wider interest in some tutorials at some point?
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jimmystones
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Re: Learning path for FPGA

Unread post by jimmystones »

I second the above comments. Personally I started by copying a feature (NVRAM save/load) from one core to another. Looking at the git diff for the changes made to implement a single feature helped me understand what was related to what. Trying to understand an entire core + framework from the start was too much for my brain to handle!

Also I found this site https://hdlbits.01xz.net/ useful for getting Verilog concepts straight in my head.
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Re: Learning path for FPGA

Unread post by Alkadian »

robinsonb5 wrote: Sun Feb 21, 2021 11:32 am I think I'd start with something simple - maybe take the MemTest core, learn to built it in Quartus, then figure out how to change the background colour and text colour. (My first project was on the Turbo Chameleon 64 cartridge - I took the hardware diagnostic core and used the graphics primitives and PS/2 mouse component to implement a simple "Pong" game.)

You're going to encounter both VHDL and Verilog - both languages have their pros and cons. VHDL will throw a compilation error for the tiniest of mistakes. Verilog will quite often march straight past the most blatantly wrong code and silently produce a non-working core as a result! For this reason, I tend to consider VHDL the better language for learning, at least until you have the base concepts secure.

The most important thing is to understand what type of logic is being described by your code, understand the difference between combinational logic and registers, and understand the difference between blocking and non-blocking assignments.

Would there be wider interest in some tutorials at some point?
@robinsonb5,

I have just found your post and I would really appreciate if you could share some tutorials whenever you get a chance. For the reasons you have rightly mentioned here, I have been thinking to go down the route of VHDL or at least for now. Indeed my goal would be to learn the basics of VHDL, Quartus and Mister framework and try to help others with their existing cores and as such try and give my little tiny contribution if I will ever reach a decent level. At least I have got a lot willingness to start with as I really feel I want to help! I understand it will take time to digest it all but again I feel ready :mrgreen:

Anyway I have already started looking at different online resources that have been kindly advised in other threads in the forum as a starting point. But 'proper' tutorials will definitely help.

Also books wise, would someone please be so kind as to advise between these two books:

https://www.amazon.co.uk/Vhdl-Example-B ... oks&sr=1-1

https://www.amazon.co.uk/FPGA-Prototypi ... ks&sr=1-18

Shall I start with the first book and then move to the second one? Or shall I invest directly on the second one?

I know I know..I can hear you and guess what..you are right I am confused :lol:

Thanks a lot!
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Re: Learning path for FPGA

Unread post by dshadoff »

The first one is mostly a description of the language, without much information on how to put it to use.
The second one should be pretty good, but uses a Xilinx board (additional expense) and Xilinx software.

The skills are transferrable but may not be exactly one-for-one when transferring to DE10-Nano.
I think that author also had an Altera-focused book, maybe check to see if it’s still available.
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Re: Learning path for FPGA

Unread post by Alkadian »

dshadoff wrote: Sun Mar 21, 2021 3:24 pm The first one is mostly a description of the language, without much information on how to put it to use.
The second one should be pretty good, but uses a Xilinx board (additional expense) and Xilinx software.

The skills are transferrable but may not be exactly one-for-one when transferring to DE10-Nano.
I think that author also had an Altera-focused book, maybe check to see if it’s still available.
Thanks for your feedback, much appreciated. Would you mind comfirming that the book below is the one you were referring to?

https://www.amazon.co.uk/Embedded-SoPC- ... 111800888X

Thanks a lot!
dshadoff
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Re: Learning path for FPGA

Unread post by dshadoff »

Yes, this looks like the one I was referring to. It's a bit old - referring to DE1 and DE2 boards - but it's Altera- and Quartus-based.

Altera likes to push their "NIOS processor" which is effectively a CPU implemented in FPGA logic, as a means of performing sequential operations... They still do this, so those skills aren't out-of-date. However, you should know that MiSTer does not use NIOS, as the DE10-Nano includes its own ARM processor implemented in hardware. So don't get hung up on the NIOS-specific aspects. It might be useful on other FPGA boards at some other time, but not in MiSTer.

In general, when starting out, I would suggest that the major points of learning won't be Verilog versus VHDL - these are really just syntaxes - but rather, a method of thinking about how to design things in FPGA logic, using clocks, sequential logic, and combinational logic.

You will be getting a lot of feedback from the "compiler"/developer software, so it is important to become accustomed to one of them first (later, once understood, these are transferrable skills to other FPGA systems and development software as well).

Major aspects of the dev software you should get accustomed to are:
- The overall process of compilation
- why clocks are special
- how to prepare testbenches/simulations
- how to use the built-in logic analyzers (SignalTap on Altera chips)
- when and how to invoke specialized hardware (i.e. "megafunctions" on Altera)

Most beginner books don't spend even a moment introducing these concepts, which is why a proper course-like textbook is useful. Unfortunately, most are written for Xilinx FPGAs... and while the skills are transferrable, the boards they suggest to use are in the $300 range... plus the book itself.

Since you (probably) already have the DE10-Nano, you should start by looking at the documents supplied by the maker, such as "My First FPGA" and the "DE10-Nano User Manual" here:
https://www.terasic.com.tw/cgi-bin/page ... 6&PartNo=4

And just remember that we use version 17.0.x of Quartus for MiSTer cores, so get that version when you download Quartus.
Bas
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Re: Learning path for FPGA

Unread post by Bas »

Love the discussion.. an additional point from this sysadmin/devops type IT geek: which foundational works on EE would be useful? While code is familiar enough, I feel like I'm sorely lacking in the EE department.
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Re: Learning path for FPGA

Unread post by dshadoff »

Um... that's a big subject. Analog electronics can really be thought of as a separate things from digital. Perhaps - unless you want to work on audio and CRT repairs - you might want to look at digital. I don't think I can really offer a good starter book though.
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Re: Learning path for FPGA

Unread post by ExCyber »

For MiSTer-type FPGA work, the most relevant topic within electrical engineering is probably "digital design", and there are various introductory textbooks about it that are HDL-oriented. Some of the older ones probably have more of an emphasis on techniques that are only relevant for ASIC designs and not so much for FPGA. I personally mostly learned the fundamentals in an academic sense from a combination of these, although I wouldn't necessarily describe them as "foundational":
  • Computer Organization and Design: The Hardware/Software Interface; Patterson/Hennessy
  • Digital Design; Mano/Ciletti
  • Advanced Digital Design with the Verilog HDL; Ciletti
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Alkadian
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Re: Learning path for FPGA

Unread post by Alkadian »

dshadoff wrote: Sun Mar 21, 2021 5:08 pm Yes, this looks like the one I was referring to. It's a bit old - referring to DE1 and DE2 boards - but it's Altera- and Quartus-based.

Altera likes to push their "NIOS processor" which is effectively a CPU implemented in FPGA logic, as a means of performing sequential operations... They still do this, so those skills aren't out-of-date. However, you should know that MiSTer does not use NIOS, as the DE10-Nano includes its own ARM processor implemented in hardware. So don't get hung up on the NIOS-specific aspects. It might be useful on other FPGA boards at some other time, but not in MiSTer.

In general, when starting out, I would suggest that the major points of learning won't be Verilog versus VHDL - these are really just syntaxes - but rather, a method of thinking about how to design things in FPGA logic, using clocks, sequential logic, and combinational logic.

You will be getting a lot of feedback from the "compiler"/developer software, so it is important to become accustomed to one of them first (later, once understood, these are transferrable skills to other FPGA systems and development software as well).

Major aspects of the dev software you should get accustomed to are:
- The overall process of compilation
- why clocks are special
- how to prepare testbenches/simulations
- how to use the built-in logic analyzers (SignalTap on Altera chips)
- when and how to invoke specialized hardware (i.e. "megafunctions" on Altera)

Most beginner books don't spend even a moment introducing these concepts, which is why a proper course-like textbook is useful. Unfortunately, most are written for Xilinx FPGAs... and while the skills are transferrable, the boards they suggest to use are in the $300 range... plus the book itself.

Since you (probably) already have the DE10-Nano, you should start by looking at the documents supplied by the maker, such as "My First FPGA" and the "DE10-Nano User Manual" here:
https://www.terasic.com.tw/cgi-bin/page ... 6&PartNo=4

And just remember that we use version 17.0.x of Quartus for MiSTer cores, so get that version when you download Quartus.
Awesome, thanks for confirming. I will go ahead then.

Also thank you very much for your additional points. Very useful indeed!

Yes I have got the DE10-Nano and a free copy of Quartus as well. Well, time to study! :mrgreen:

Thanks again!
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Re: Learning path for FPGA

Unread post by jca »

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Alkadian
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Re: Learning path for FPGA

Unread post by Alkadian »

jca wrote: Sun Mar 21, 2021 8:00 pm Interesting Lecture:
https://opencores.org/usercontent/doc/1262707254
Thanks for that! That looks a good source indeed!
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Re: Learning path for FPGA

Unread post by jca »

I am a semi-noob in regard to FPGA and being able to compile existing cores is a good start.
But I have a question: this weekend I was looking at the Vectrex core and compiled it, it works but its size is different from the official one although I used the latest release and used Quartus 17.0.2. Is this normal or should I get the exact same size?
Official one: 3,708,364.
Mine: 3,722,624.
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Re: Learning path for FPGA

Unread post by dshadoff »

I wouldn't worry about the exact sizes.
There are a number of factors, including the fact that you are almost certainly using the Lite version whereas the official release usually comes from the Standard version of the tool.

As long as:
- you are using the official sources
- the compile is successful and
- timing issues aren't pointed out during compilation
...you should get the same results as the official core
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Re: Learning path for FPGA

Unread post by Lightwave »

dshadoff wrote: Sun Mar 21, 2021 5:08 pm Most beginner books don't spend even a moment introducing these concepts, which is why a proper course-like textbook is useful. Unfortunately, most are written for Xilinx FPGAs... and while the skills are transferrable, the boards they suggest to use are in the $300 range... plus the book itself.
The strange thing is, we keep hearing that the DE-10 is targeted towards education (and is partially subsidized for that purpose), therefore you would think there would be a wealth of learning materials available for it if this is the case.
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Re: Learning path for FPGA

Unread post by jca »

dshadoff wrote: Mon Mar 22, 2021 9:12 pm I wouldn't worry about the exact sizes.
There are a number of factors, including the fact that you are almost certainly using the Lite version whereas the official release usually comes from the Standard version of the tool.

As long as:
- you are using the official sources
- the compile is successful and
- timing issues aren't pointed out during compilation
...you should get the same results as the official core
Thanks.
Previously I compiled some cores which worked but never paid attention to the size.
This time I wanted to be more meticulous and noticed the difference. The core seems to work properly so I was not really worried, just curious.
And yes I am using the Lite version.
dshadoff
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Re: Learning path for FPGA

Unread post by dshadoff »

Lightwave wrote: Mon Mar 22, 2021 9:23 pm
dshadoff wrote: Sun Mar 21, 2021 5:08 pm Most beginner books don't spend even a moment introducing these concepts, which is why a proper course-like textbook is useful. Unfortunately, most are written for Xilinx FPGAs... and while the skills are transferrable, the boards they suggest to use are in the $300 range... plus the book itself.
The strange thing is, we keep hearing that the DE-10 is targeted towards education (and is partially subsidized for that purpose), therefore you would think there would be a wealth of learning materials available for it if this is the case.
There is hardly a wealth of materials for any FPGA in terms of textbooks. Each vendor creates some initial startup material for people though. And because of the nature and complexity of these devices, they are expected to be used in a University setting, where many professors create their own materials.

And of course, they aren't really mainstream yet. It looks like that day will come though.

In the meantime, one can always read datasheets and application notes from the vendors - but those often assume that you are already familiar with concepts.
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Re: Learning path for FPGA

Unread post by bellwood420 »

jca wrote: Mon Mar 22, 2021 9:31 pm Previously I compiled some cores which worked but never paid attention to the size.
This time I wanted to be more meticulous and noticed the difference. The core seems to work properly so I was not really worried, just curious.
And yes I am using the Lite version.
I'm curious, too.
As @dshadoff saying, there will be no problem in functionality as long as we don't get any timing issues, though.

In my environment(version 17.0.2.602 Lite edition), Quartus outputs rbf of 3,708,364 bytes.
The size are the same as officially released one but its content is not exactly the same.
I can understand this difference may be due to different edition(Lite/Standard).
But why isn't mine the same as @jca's?

Recently, I made a little fix on Arcade-MoonPatrol and provided the rbf on this forum.
At the same time, someone built a rbf including my fix and provided it on discord.
Two rbf files were exactly the same.

I'm assuming that the same sources, same qsf, same version, same edition will generate the same binary.
Am I wrong?

-----
EDIT:

The result shown above were done on Windows.
I tried building on Ubuntu with Quartus version 17.0.2.602 Lite edition.
I got rbf in different size(3,709,408 bytes) and content.

-----
EDIT:

I noticed that auto generated string(BUILD_DATE in build_id.v) is included in rtl source.
This can change fitter initial routing and make binary different.

I got different rbf by tweaking system date.
It must be the main reason ;) So, rbf can change every day.

In other words, it can be said that we get the same rbf on the same day with the same sources, same OS, same Quartus version, same Quartus edition.
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Re: Learning path for FPGA

Unread post by dshadoff »

There is an element of randomness required during the fitting operation, which could provide varied results.
You may also find that certain cores have slightly different timings for the same code, same computer, same Quartus, but two different executions (this would certainly be due to different arrangements of the elements, which would end up with different binary outputs).

I suggest not to get hung up on it.
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Re: Learning path for FPGA

Unread post by bellwood420 »

dshadoff wrote: Tue Mar 23, 2021 4:47 am There is an element of randomness required during the fitting operation, which could provide varied results.
Of course the fitting operation requires randomness, but I don't think it's completely random. It is pseudo random.
If we have exactly the same sources, the same Quartus, the same settings, and the same seed value, we should get the same result, I think.
As I added to my earlier post, build date is embedded in source, so the source changes from day to day.
As a result, the behavior of fitter will change even if the sources in /rtl /sys directory and emu module have not been modified.

EDIT:
I confirmed that I got the same binary as official release 20210303 with the same BUILD_DATE string("210303").
So edition does not matter at least.
I understand it is meaningless to pursue binary sameness, though :)
robinsonb5
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Re: Learning path for FPGA

Unread post by robinsonb5 »

bellwood420 wrote: Tue Mar 23, 2021 5:17 amOf course the fitting operation requires randomness, but I don't think it's completely random. It is pseudo random.
It is indeed pseudo-random - and you can even tweak the seed if you wish!
(Assignments -> Settings -> Compiler Settings -> Advanced Settings (Fitter)... -> Initial Placement Seed.)
If you have a codebase which misses timing closure by a whisker, or fails to fit by a whisker, it can be useful in a last-resort kind of way to tweak this seed and re-roll the dice. As you've already noticed, though, the tiniest, most trivial change in the codebase will re-roll them, too - I have a hunch that the actual seed is some kind of hash of the Synthesis results, combined with the user-specified seed.
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Re: Learning path for FPGA

Unread post by MISTerMark »

Not sure if its any good but I've seen Nandland mentioned a few times on reddit when beginners are asking to get started.

https://www.nandland.com/
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