Arlet 6502 Core

Discussion of developmental aspects of the MiSTer Project.
nico24
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Arlet 6502 Core

Unread post by nico24 »

Is it possible to use the low PHI clock cycle for RAM access with the Arlet 6502 core - as in a real 6502 chip? Most cores (maybe all) I have seen just split the VRAM circuitry from the operation of the 6502 core, but I'd be interested to know if you can indeed mimic actual hardware ram/rom timing or it's not actually possible.

Thanks,
Nick
nico24
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Re: Arlet 6502 Core

Unread post by nico24 »

The answer by the way, is no, it's not.
nico24
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Re: Arlet 6502 Core

Unread post by nico24 »

I'm going to do an upcoming video about how to get over this with the 6502 core.
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macro
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Re: Arlet 6502 Core

Unread post by macro »

FPGA (Quartus?) seems to dislike using signals from components as clocks and complains about them. (unlike real hardware)

instead I find you have to pick a higher clock to clock everything related on, and use enable signals to only select the relevant clock pulses.
Did I do something useful?

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