There are a lot of shorthands that you aren't likely to get people to change (as in: they are conventions that you'll need to learn), and yet there are lots of things which could make the code easier to understand. (But I frequently have similar comments about other peoples' software as well...)
One item that really doesn't cost anybody anything, would be to name things clearly....
1) If RESET is active low, it should be named RESET_N, or at least commented at the interface portion at the top of the file
2) Super-short variable names are not helpful to anybody. 'V' can be 'video', 'vertical', 'volume', or may simply be the next variable after 'U'...
There are also inevitably going to be some complex-looking logic AND/OR/etc. expressions at points in the code, which are going to be unclear at first glance what they accomplish. Placing a small comment next to these would be incredibly helpful for the next person.
Learning to develop a new MiSTer core
Re: Learning to develop a new MiSTer core
Thanks @nullobject, really appreciated.
I am beginning my way into all of that hardware world and started a hack computer with VHDL, now trying to run it on Mister.
Now I am struggeling if I should now do everything again in Verilog. I have a hard time to understand anything in any of the cores that are implementing a simple vga screen as that section is in Verilog and it is very hard to read.
Verilog reminds me on pearl. You can do very short code, that no one else can read anymore. So currently I like VHDL more because it is much better to read and understand for a beginner like me.
I even had a hard time to understand when a new module is loaded and where it is defined, before I understood that you just call it in Verilog and dont specify it before.
So I believe that is quite typical for a beginner in hardware design but it is so confusing.
I am beginning my way into all of that hardware world and started a hack computer with VHDL, now trying to run it on Mister.
Now I am struggeling if I should now do everything again in Verilog. I have a hard time to understand anything in any of the cores that are implementing a simple vga screen as that section is in Verilog and it is very hard to read.
Verilog reminds me on pearl. You can do very short code, that no one else can read anymore. So currently I like VHDL more because it is much better to read and understand for a beginner like me.
I even had a hard time to understand when a new module is loaded and where it is defined, before I understood that you just call it in Verilog and dont specify it before.
So I believe that is quite typical for a beginner in hardware design but it is so confusing.
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Sorgelig
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Re: Learning to develop a new MiSTer core
Verilog is pretty close to C.
If you are long time C developer, then with a little HDL introduction you should be able to read Verilog. Pretty much 1:1 with some adjustments to HDL specifics.
Same VHDL is basically Pascal for HDL. If you plan to write in VHDL, then try not to change variable cases, as VHDL being very strict language completely ignores the variable case making sometimes hard to read. Some developers like to write in a single module RESET, reset, Reset. This is hard to read. Many text editors with auto highlighting of the same word don't work with mixed cases.
If you are long time C developer, then with a little HDL introduction you should be able to read Verilog. Pretty much 1:1 with some adjustments to HDL specifics.
Same VHDL is basically Pascal for HDL. If you plan to write in VHDL, then try not to change variable cases, as VHDL being very strict language completely ignores the variable case making sometimes hard to read. Some developers like to write in a single module RESET, reset, Reset. This is hard to read. Many text editors with auto highlighting of the same word don't work with mixed cases.