Lets actually try Hybrid Emulation

[robinsonb5]

One thing to bear in mind: when the Amiga first starts up the Kickstart ROM is overlaid at location zero (until the relevant bit is cleared with a write to one the CIA registers) - the "Minimig" path knows how to handle that, but the direct-to-SDRAM path doesn't - so you should take the "minimig" path for Chip RAM accesses at bootup until the overlay's cancelled. I'm not sure how that's signalled to the CPU wrapper on MiSTer - I'll take a look...

Edit: OK - it looks like the fast path for chipram and kickstart is disabled via the cachecfg signal, the lower two bits of which are controlled by the kickstart overlay - so as long as you're using the slower "minimig" path any time the TG68 would have used it, this shouldn't be causing your problem.

[foft]

I think perhaps the mem_ready, chip_ready is controlled by some of the things I'm outputting. I'm trying remove that from my cpustate signal, so cpustate is driven from registers only.

[foft]

Its going to work this time, its going to work this time! I think that every time

[jca]

So far you made incredible progress in the blink of an eye.

[foft]

We have workbench. Repeat, we have workbench!!

Many thanks for the help/advice @robinsonb5!

[jca]

One week since your original post
Did you get any sleep lately?
Congratulations!

[foft]

So, ran sysinfo. Says its only half the speed of a 68040! Hmmm....

[robinsonb5]

We have workbench. Repeat, we have workbench!!

That's just awesome news - well done!

FPGA history is being made in this thread!

[robinsonb5]

So, ran sysinfo. Says its only half the speed of a 68040! Hmmm....

From (turbo) Chip RAM or ARM-side Fast RAM?
Didn't you say you were using Musashi? That doesn't do JIT, or does it?

As a baseline can you run a Dhrystone or something entirely ARM-side to see what the emulator itself is capable of on the SoC?

[foft]

Well I have 8MB fast ram set up arm side.

Yes Musashi, looks like it pre-compiles a jump table then runs through those.

Yeah, investigating:-)

[foft]

I actually don't have any vhd setup yet, so its all off adf files. Need to work out how to get lha archives on here!

Let me wire up reset then I'll upload a version to play with.

[foft]

OK, here is the github fork for the hardware:
https://github.com/scrameta/Minimig-AGA_MiSTer

Here is also the latest test core.

NB how to use:
i) Start new core from the menu
ii) Set core to 68020, 2MB chip, 8MB fast and reset
iii) ssh into mister and start ./musashi_68020_mister

Should now work. Though when you reset it you currently need to restart musashi_68020_mister. I need to finish plumbing in reset.

Clearly very early version so likely lots won't work.

[foft]

So tomorrow evening:
i) Wire up reset to make it less annoying to use!
ii) Wire up some settings so you can e.g. select fast ram
iii) Try to make it faster

[ByteMavericks]

That’s inspiringly awesome! Would love to get started with fpga stuff...

[foft]

Tomorrow I’m going to try out Michal Schulz’s Emu68
https://github.com/michalsc/Emu68
Wish me luck!

[kolla]

Where is the Sysinfo screenshot!

[Neocaron]

Tomorrow I’m going to try out Michal Schulz’s Emu68
https://github.com/michalsc/Emu68
Wish me luck!

Good luck!
You're creating history here, a lot of cores impossible now because of the lack of space (or frequencies too low) on the FPGA chip would become possible in this hybrid approach.
Some would call that heresy, I call that pushing boudaries and being smart! Congrats!

[allyourbasekris]

Where is the Sysinfo screenshot!

I just tried it out and got to Workbench and took you a nice screenshot.

Screenshot (4).png (580.41 KiB) Viewed 7205 times

[Neocaron]

Where is the Sysinfo screenshot!

I just tried it out and got to Workbench and took you a nice screenshot.Screenshot (4).png

BEAUTIFUL

[lordoftime79]

how do i start musashi_68020_mister?

[lordoftime79]

Can you please tell me how to use this - I dont know anything about ssh so where does the file go and how do I run it?

[jca]

Can you please tell me how to use this - I dont know anything about ssh so where does the file go and how do I run it?

I think it is better for you to wait until something more usable is posted. Right now it is a proof of concept, which is a huge step, but my guess is that you will be frustrated in no time.

[lordoftime79]

i just want to look i am excited if I had some instuctions i cud follow them.

[foft]

Download 7-zip
Extract the tar to get the two files

Download winscp
Connect to mister with winscp
- drag the musashi_68020_mister to /media/fat
- drag the core to /media/fat/_computer/ (with the other cores, I might have the name wrong)

Download putty or mobaxterm
Connect to mister with putty
cd /media/fat (then enter)
./musashi_68020_mister (then enter)

Worth a read:
https://www.jamesfmackenzie.com/2021/01 ... ing-files/

This will all be made simpler

[allyourbasekris]

i just want to look i am excited if I had some instuctions i cud follow them.

https://schh.medium.com/ssh-for-dummies-ea168e6ff547

[SpacemanX]

Absolutely amazing progress! It's hard to fathom that you have got this working in such a short time.

To me Buffee looks similar to this approach on ground level. They are claiming close to 100x performance target to what is achieved here currently. I do understand that it's still very very early days, but it got me wondering what is the theoretical performance level achievable with de10-nano cpu/fpga combo?

[foft]

Question for people who know Amiga JIT options... Which is best to try:
Aranym uat_cpu: https://github.com/aranym/aranym/tree/m ... rc/uae_cpu
Emu68: https://github.com/michalsc/Emu68
TomB's Pandora uae4arm: https://github.com/PandTomB/uae4arm

None of them are as well documented as musashi, but I'll have a go at figuring out how to use them.

I'm thinking the last one is the best option, since the gp32/gp2x/openpandora devs were super at doing arm optimisation.
I remember this one was used a lot, though its interpreted iirc and only 68000.
https://github.com/notaz/cyclone68000

One complication in all this is that the hps-fpga bridge is little endian, at least in how it automatically handles misaligned accesses. If all the accesses are aligned then I could put big endian format through it to avoid the conversion arm side (fpga side is basically 'free').

[lordoftime79]

nice work. unfortunately even following your insturctions it wouldnt work for me, just got a blue and purple garbled screen.

[foft]

nice work. unfortunately even following your insturctions it wouldnt work for me, just got a blue and purple garbled screen.

Yeah you need to start it in the right order.
e.g. set to 8MB fast ram, reset on the core. THEN start the cpu process.

[foft]

Absolutely amazing progress! It's hard to fathom that you have got this working in such a short time.

To me Buffee looks similar to this approach on ground level. They are claiming close to 100x performance target to what is achieved here currently. I do understand that it's still very very early days, but it got me wondering what is the theoretical performance level achievable with de10-nano cpu/fpga combo?

Their work is open so we'll be able to use their pjit when its working. Actually I think they expect their approach to be slower than standard jit, just with fewer 'jitters'.

Not sure how the Buffee CPU compares to the ARM Cortex A9 @800MHz here.
Edit: Looked it up: Octavo OSD335x-SM with ARM Cortex A8 AM335x @ 1GHz.

Should be pretty comparable I'd have thought, the A9 has a shorter pipeline.