JasonA wrote: ↑Mon Dec 05, 2022 1:50 pm
Most of the changes I made to the Oric core earlier this year were in attempts to get TAP loading supported through the OSD. It required a bit of conversion to Verilog from VHDL in order to simulate the core on Verilator. My initial approach to parse the TAP format and bypass traditional cassette loading methods was getting too complicated so I went back to a cassette loading approach. The comparisons with ADC took longer than anticipated and my timing was off. Thankfully, Flandango stepped in to help me out. As many of you know, Flandango really understands how cassette loading signals and timing work, and hats off to him for getting this feature in place.
I will sync with Flandango to simply get the TAP support added to the official repo I think, as most of my code is related to Verilog, and not really needed on the official repo.
Hopefully this TAP functionality will be in the main repo soon.
Thanks to all of you for testing this important and sought after feature.
The source code on mister's github is old and has a bug in the disk controller. Rampa has been waiting for months for Sorgelig to approve the pull requests that he has continued to make in the core. I suggest you use the source code from here: