PistolsAtDawn wrote: ↑Mon Apr 14, 2025 5:26 pm
I would be curious to know how the level of effort for your solution compares to "basically a full re-write" (which is how adding save states to the core was discussed in recent years). Was this a new layer/module that you fit into the current core, or did it require a lot more than that?
A full rewrite is a bit of an exaggeration but for the save states method like the other cores everything in the core needs to be able to be paused. That means adding a pause signal for all parts of the core.
I wanted to add save states with as few changes to the core as possible. The current method is waiting for an interrupt and when the CPU reads the interrupt address it overrides the ROM data and runs the save state code. The state of the CPU is restored at the end of the interrupt handler and this means the CPU did not need any modifications for save states.
The PPU was also unmodified in the beginning because I used shadow registers to save the write-only registers. This cost a lot of logic and there was an issue with the cart bus so instead I modified the PPU to allow for reading the write-only registers during a save state.
I did have to make a lot of changes to the sound chip because it needed to be paused and almost nothing of the internal state can be read by the CPU.
All the cartridge chips like DSP/SA1/Super FX also needed to be modified to be able to read the state.
Since all the state loading/saving is done in CPU code, it does require writing a lot of assembly code too.
thanks!