Porting a new core
Posted: Sun Oct 04, 2020 10:23 am
Hi all,
I have been working on my FPGA programming, presently using a language called Silice to get me started, but have now done some playing in verilog.
I have a 'kind of' working j1eforth running on the de10nano using the MiSTer VGA port on the I/O board, communicating via a UART attached to the USER PORT pins. https://github.com/rob-ng15/Silice-Play ... r/DE10NANO
I'd like to start porting this to MiSTer to aid in my experience, but I am struggling with getting a 640x480 50hz display. I've looked at the template from the wiki. Does anyone have any suggestion as to the best template or core to start from with the 640x480 50hz display?
Many thanks, Rob.
I have been working on my FPGA programming, presently using a language called Silice to get me started, but have now done some playing in verilog.
I have a 'kind of' working j1eforth running on the de10nano using the MiSTer VGA port on the I/O board, communicating via a UART attached to the USER PORT pins. https://github.com/rob-ng15/Silice-Play ... r/DE10NANO
I'd like to start porting this to MiSTer to aid in my experience, but I am struggling with getting a 640x480 50hz display. I've looked at the template from the wiki. Does anyone have any suggestion as to the best template or core to start from with the 640x480 50hz display?
Many thanks, Rob.