ao486 core and SDRAM performance
Posted: Tue Dec 08, 2020 7:28 pm
Although I am talking without having checked the SDRAM controller used in ao486, I think these data may be of interest to the developer.
I recently upgraded my SDRAM controller to work with bank interleaving to keep the SDRAM as busy as possible. I operate it with 2-word bursts, so my base case is 8 cycles per access and 4 bytes of output data. I commonly run it either at 48MHz or at 96MHz. Without bank interleaving, I can obtain 48MB/s. With bank interleaving, it can go much higher than that (126MB/s). Please read the following data
These are random read tests across the four banks. Data throughput increases by 2.6x with bank interleaving. But, I want to call your attention about the third row that only gets a 1.5x benefit despite using bank interleaving. That third row is what can be achieved with MiSTer memory modules as they have been produced in the last few months. There was a design change that shorts pins A12/A11 to data mask pins DMH and DML. This limits programming banks in parallel with bank reads and pulls down performance.
I think that, as of today, maybe the ao486 core is the only one which could benefit from restoring the DMH and DML signals to independent connections. Maybe the ao486 core is getting high speed by using very large burst reads. As I said, I haven't looked into the details. But I thought it was worth sharing this information here.
Note that other future cores, such as PSX, may actually need this kind of performance. So limiting memory modules by shortening DMH/L may not be a good long term strategy.
I recently upgraded my SDRAM controller to work with bank interleaving to keep the SDRAM as busy as possible. I operate it with 2-word bursts, so my base case is 8 cycles per access and 4 bytes of output data. I commonly run it either at 48MHz or at 96MHz. Without bank interleaving, I can obtain 48MB/s. With bank interleaving, it can go much higher than that (126MB/s). Please read the following data
Code: Select all
Case | SDRAM clock | Burst Length | Data throughput
No bank interleaving | 96 MHz | 2 | 48 MB/s
Bank interleaving | 96 MHz | 2 | 126 MB/s
A12/A11 = DMH/DML | 96 MHz | 2 | 71 MB/s
I think that, as of today, maybe the ao486 core is the only one which could benefit from restoring the DMH and DML signals to independent connections. Maybe the ao486 core is getting high speed by using very large burst reads. As I said, I haven't looked into the details. But I thought it was worth sharing this information here.
Note that other future cores, such as PSX, may actually need this kind of performance. So limiting memory modules by shortening DMH/L may not be a good long term strategy.