SDRAM Reliability

optyfr
Posts: 1
Joined: Sun May 24, 2020 8:36 pm
Has thanked: 2 times

Re: SDRAM Reliability

Unread post by optyfr »

Don't worry, JT will find a solution to make CPS 1.5 to work with most of current SDRAM modules, but maybe a very little % of users will still get troubles with it (but those should also fail probably with the official memory test). Although, take it more as a warning for future cores that will require more and more BW with SDRAM...
User avatar
Alkadian
Top Contributor
Posts: 721
Joined: Thu May 28, 2020 9:55 am
Has thanked: 289 times
Been thanked: 116 times

Re: SDRAM Reliability

Unread post by Alkadian »

Alkadian wrote: Sat Dec 26, 2020 10:58 pm First of all thank you so much Jotego for your very much appreciated hard work!

Well, I am also one of the lucky ones with no ram issues at all apart from Slammasters which it won't boot. Infact I have got two mister setups with two 128mb ram modules. So I consider myself double lucky :mrgreen:

Anyways regarding the PSU query I have got mine which is a Mean Well unit rated @ 5v, 4A, 20W and again no issues so far...touch wood :D
Thanks Jotego! With the latest telease of the core, Slammasters runs perfectly fine! :mrgreen:

EDIT: I have spoken too early, after the first stage I have got illegal instructions error messages, but at least now it boots up! :D
MostroW
Posts: 323
Joined: Tue Aug 18, 2020 3:32 pm
Has thanked: 140 times
Been thanked: 43 times

Re: SDRAM Reliability

Unread post by MostroW »

That's kind of a hard demand of someone who puts in his personal time?
If Jotego (or any other author for that matter) had any interest of sharing his / her work then they would've made it public.

Also i think he has made a lot of his work opensource, just check his signature for his git.


EDIT:
Did someone just remove his post or did he remove that himself?
galibert
Posts: 5
Joined: Sun Jan 03, 2021 9:43 pm

Re: SDRAM Reliability

Unread post by galibert »

Sorgelig wrote: Sun Dec 27, 2020 6:00 pm Aside from SDRAM...
I was wondering, why sdram? synchronous static ram would give you an access every cycle, it seems (pipelined), and memory bandwidth on random access is a real problem, especially for arcade...

OG.
MadDog
Posts: 55
Joined: Sat Jun 20, 2020 9:30 pm
Has thanked: 31 times
Been thanked: 31 times

Re: SDRAM Reliability

Unread post by MadDog »

jotego wrote: Fri Dec 25, 2020 5:22 pm
lamarax wrote: Fri Dec 25, 2020 4:31 pm I still have to ask though; what happened with the Street Fighter (Capcom 68000) core, and why this doesn't boot for anyone after having been updated to run @ 48Mhz, a measure taken to supposedly bypass the objective problems that you're describing re: existing 128MB modules?
I was in a rush and uploaded the wrong file. Apologies about that.
Ah. Glad I looked for a post about this... I didn't see a bug reported on the jtsf core about Street Fighter not booting after the latest update. Please don't feel rushed - I'm just glad it's not just me and Jotego is aware. Fantastic work. Take your time, and thank you (and literally every other core developer) for the nostalgia!! :D
User avatar
jdeberhart
Posts: 40
Joined: Sun Jun 21, 2020 11:41 pm
Been thanked: 5 times

Re: SDRAM Reliability

Unread post by jdeberhart »

galibert wrote: Sun Jan 03, 2021 9:45 pm
Sorgelig wrote: Sun Dec 27, 2020 6:00 pm Aside from SDRAM...
I was wondering, why sdram? synchronous static ram would give you an access every cycle, it seems (pipelined), and memory bandwidth on random access is a real problem, especially for arcade...

OG.
Because SRAM is stupidly expensive for anything more than a few hundred kilobytes. You'd easily be looking at $500+ USD for a 128 MB SRAM module.
User avatar
jotego
Core Developer
Posts: 61
Joined: Sun May 24, 2020 7:07 pm
Has thanked: 22 times
Been thanked: 205 times

Re: SDRAM Reliability

Unread post by jotego »

I received a couple of weeks ago some SDRAM boards using the v2.9 design. This version uses a voltage regulator and has other improvements to prevent some of the issues discussed above. I have not found problems so far and measuring the memory supply voltage, is most of the time around 3.3V, with occasional peaking at ~3.7V and 2.8V. Remember that we were seeing peaks at 4.04V (max) and 2.38V (min) before and that the specification is 3.3±10%. So the voltage ripple is much better now and should not be a problem.

Although I have used several boards, I have only measured one. The voltage seen is across the capacitor besides device U4 (the voltage regulator).

Thanks to Nathan from MiSTer FPGA UK for the samples.
SDRAM v2.9 VDD-VSS.png
SDRAM v2.9 VDD-VSS.png (35.45 KiB) Viewed 4252 times
Open IP for many chips in my github account
RBF files for my MiSTer cores in jtbin
Support new IP and core development here
Post Reply