MiSTer FPGA Forum

Found in the Mame forum : https://forums.bannister.org/ubbthreads ... Post118692
https://github.com/jdesiloniz/svpdev/wiki/Internal-ROM
Do you think it can help to improve accuracy for the game Virtual Racing on genesis core ?
Thanks,

Hi! I'm the "author" of this dump and the repo posted above. I was planning to post some of my research here once I got more "proper" data regarding my tests on the SVP hardware, but got kinda late .

I've also been researching on timings this weekend (this is still a WIP, but...) I got some data regarding how fast code run from the IRAM (and the internal ROM) is compared to the external ROM, and also was able to measure the timing of one instruction with the oscilloscope. I'm hoping that once I measure all instructions more accurate data regarding the timings could be inferred and help in emulation.

Please let me know if you need additional details or if you want me to perform some kind of tests in the real SVP if that helps with the current emulation of the chip.

Thanks!

Hi @javitaiyou,

Thank you for your work and research on SVP hardware.
This post is to inform the community about your work.

I'm not a FPGA developer but I think your work may help to improve the SVP implementation in VHDL : https://github.com/MiSTer-devel/Genesis ... er/rtl/SVP

Thanks @wark91 for spreading the word!

I'd love to help on the actual implementation of the SVP but I don't know any VHDL (only Verilog) and my FPGA skills are not that good yet. Fun fact: this whole research started after I failed building an SVP-capable development cartridge using an FPGA running my own core of the SVP - which I started some months before the MiSTer version was released. I'm happy that it led to this though, as having got access to run code in the actual chip itself can lead to information hard to get otherwise .