MiSTer FPGA Forum

I have a rather strange issue going on. I have a simple core, that has only 1 input an 18 MHz clock from a top module. This clock is derived from a PLL that creates it from the 50 MHz system clock.
With that one clock input and my core code I get the following response - essentially the maskable interrupt irq_n goes low, and there is an associated program driven interrupt acknowledge - n_pre2.
Now if I use the MiSTer framework and pass the same clock 18MHz to the same core code through the emu.v module, into my instantiated core code I get the following:
This time no irq_n triggering.
I'm sure that this is an oddity in my code, but my general question is - has anybody seen this behavior before, of the core code acting differently when adding it into the MiSTer framework, and has there been any things to look out for that may be a typical cause of such issues?

Note - you can disregard the nmi trace, that was just captured at a different time in the cycle, and is present on both.

Broadly speaking - I've noticed also, that if I pass an actual IO pin to my reset circuit I get good behavior, but the framework IO is not direct from the pin (based on linux triggering?).

Any help appreciated.
Nick

The answer to the above - thanks to the birdybro on discord - is that I was using two different files incorrectly. The lesson here is to double-check the files you are using are correct first! Well maybe 10th, but don't waste a week before you check!