Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

somhi
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Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

In parallel with the MiSTer development I'm currently porting and updating the PCXT core to other non MiSTer FPGAS. The aim is to allow people who don't own a MiSTer to help in the development of the core, and port those improvements back to the MiSTer PCXT core.

Currently I'm maintaing at https://github.com/somhi/PCXT_DeMiSTify the following direct ports for:

  • Altera Max 10 - DECA FPGA
  • Altera Cyclone IV - NeptUNO FPGA
  • Altera Cyclone V - SoCkit FPGA

The port is nearly the same for all three boards and is made with a fantastic tool called DeMiSTify to support porting MiST cores to other boards. Porting from MiSTer requires a more initial effort but after that porting to any FPGA supported by DeMiSTify is easy.

PCXT could be ported without too much effort to any Altera FPGA with SDRAM and enough BRAM resources to handle the core. Porting to Xilinx FPGAs would require more effort, as it seems all System Verilog code must be recoded to Verilog.

The main stopping factor to universalize the PCXT core is to move BIOS and VRAM into the SDRAM controller. Until that only a few FPGA boards can handle the core, while others would work but with reduced specs (e.g. DECA port cannot handle Tandy graphics as it can only fit 32 kB for CGA in BRAM). This is well explained by @spark2k06 in Saving BRAM To Facilitate Ports and New Developments thread.

I'm also maintaining a MiSTer compatible port for Cyclone V - SoCkit FPGA at https://github.com/sockitfpga/PCXT_SoCkit/

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

New port to CYC1000 FPGA (Cyclone 10 LP).

Thanks to Kitune-san new BIOS loader into SDRAM, now it was possible to run PCXT on a 25 kLE, 76 kB (608256 bits) [66 M9k blocks] memory FPGA.

It has MDA video output only though, as 61 M9K blocks are used of a total of 66. CGA 32 kB alone requires 64 additional blocks.

If someone wants to have a look it is in the atlas branch currently https://github.com/somhi/PCXT_DeMiSTify ... /atlas_cyc
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by Newsdee »

somhi wrote: Thu Sep 22, 2022 9:54 pm Thanks to Kitune-san new BIOS loader into SDRAM, now it was possible to run PCXT on a 25 kLE, 76 kB (608256 bits) [66 M9k blocks] memory FPGA.
Would this allow for a MiST port? (if one wasn't done yet)
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

I think so. Latest compilation used 60 M9K blocks. How many does it have MiST ?
Don't have a MiST myself neither Quartus 13 but could try to prepare the missing files for the MiST project if you want to test it.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by Newsdee »

somhi wrote: Fri Sep 23, 2022 11:59 pm Latest compilation used 60 M9K blocks. How many does it have MiST ?
It has 66, so looks like it should work
https://github.com/mist-devel/mist-board/wiki/TheBoard

I think I still have Quartus 13 installed in an old PC, so I can load the file and run a compile.

How does it read HDD images though? Do we need a physical serial drive? I can at least check it boots on my MiST, though.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Ok, I have prepared by hand the MiST version, but it is uncompiled so surely some errors would need to be solved.

https://github.com/somhi/PCXT_DeMiSTify/tree/devel/mist

* HDD image should be passed by Serial cable with serdrive app.
* CGA not implemented due to lack of BRAM in this board.
* Open OSD with F12 key. Go to Video and change CGA to MDA output. The Splash screen should appear. Then Load XT BIOS ROM (and XTIDE 16 kB if not included in the main BIOS) and Reset from OSD.

NOTES ABOUT ROMS:
* Not all ROMs work with MDA video: (YUKO ST and PCXT31 works), (TANDY, micro8088, IBM5160, full XTIDE BIOS do not work)
* If you load a BIOS that does not work with MDA you need to power cycle the board.
* Sometimes a double Reset is needed (that might be outdated with the latest BIOS Loader by kitune-san)

Let's see if it works!
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

The MiST core has been sintesized by a colleague who has Quartus 13 installed.
First he had to change to another monitor because the MDA resolution at 70 Hz it does not work in all monitors.
OSD and Splash screen works. But after loading ROM from OSD and doing Reset it does nothing.
If someone else can try and give a hand :)

UPDATED: core has been updated to latest BIOS loader from MiSTer core. If anyone could try this new version let us know if it works.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by Newsdee »

somhi wrote: Sat Sep 24, 2022 9:13 pm First he had to change to another monitor because the MDA resolution at 70 Hz it does not work in all monitors.
Would CGA fit if MDA is removed? (maybe a compiler flag so both variants can be done)
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

No way to fit the CGA VRAM into MiST BRAM. 32 kB for CGA represents 64 M9k blocks and MiST has only 66.
The only viable way is to transfer the VRAM into the SDRAM.
Hope @kitune-san would tackle this at some point.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Good News. MiST port is currenly working and loading BIOS with MDA video output.
It lacks external UART port so at the moment loading operating system is not supported.
PCXT_mist_20220925.rbf
(327.66 KiB) Downloaded 113 times
MiSTica FPGA which is nearly identical to MiST should work with this same binary and it does have UART pins to load OS.

SiDi port (another MiST variant) is also available and working.

All these ports are available at the repository https://github.com/somhi/PCXT_DeMiSTify

* Altera Max 10 - DECA FPGA
* Altera Cyclone III - MiST, MiSTica
* Altera Cyclone IV - NeptUNO FPGA, UAreloaded, SiDi
* Altera Cyclone V - SoCkit FPGA
* Altera Cyclone 10 LP - CYC1000 FPGA with Atlas addon
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

I have migrated the KFPC-XT code based on SystemVerilog used in MiSTer, to Verilog, thanks to the tool sv2v by Zachary Snow:

https://github.com/spark2k06/PCXT_MiSTe ... FPC-XT/HDL

This is necessary to bring the core to older systems based on the Xilinx platform, as ZXUno.
kitune-san wrote:
@kitune-san, I'd still need to add all the comments from your original project, but if you could do a quick check to make sure everything fits, I'd appreciate it ;-)
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

Maybe this is it?
https://github.com/spark2k06/PCXT_ZXUno ... HW/KFPC-XT

KF8237 (DMA) is changed in the FDC test branch.
I would recommend updating when needed.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote: Tue Sep 27, 2022 2:07 pm Maybe this is it?
https://github.com/spark2k06/PCXT_ZXUno ... HW/KFPC-XT

KF8237 (DMA) is changed in the FDC test branch.
I would recommend updating when needed.
Yes, sorry, this is the repository where I have moved it to verilog... thank you.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

I'll take a look when I have time. I think it will be very time consuming.

When operation is unstable, first suspect timing constraints.
Basically, expect the operation to be unstable without timing constraints.
For example, using a clock that is not output from the DCM, will it be placed correctly?
What is the treatment between clocks that are not synchronized?

Unfortunately I do not have a Xilinx board...
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote: Tue Sep 27, 2022 3:19 pm I'll take a look when I have time. I think it will be very time consuming.

When operation is unstable, first suspect timing constraints.
Basically, expect the operation to be unstable without timing constraints.
For example, using a clock that is not output from the DCM, will it be placed correctly?
What is the treatment between clocks that are not synchronized?

Unfortunately I do not have a Xilinx board...
Don't worry, I hope that someone in the developer community can collaborate on this, I'm sure we will all benefit from it.

I don't have much experience, but I will take your advice into account.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Newsdee wrote: Sun Sep 25, 2022 11:45 am Would CGA fit if MDA is removed? (maybe a compiler flag so both variants can be done)
Yes it should fit. I already compiled for CYC1000 and SiDi which both have 66 M9K memory blocks the same as MiST.

Anyone wanting to try just need to compile source project in MiST folder from https://github.com/somhi/PCXT_DeMiSTify

Using vendor-specific Altera RAM2P IP modules saves half the BRAM used for VRAM.
That way I could allocate 128 kB CGA in Neptuno, UAreloaded, Deca FPGAs and 16 kB CGA in Atlas CYC1000, SiDi and MiST.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Now should be possible to play some Tandy 1000 games on MiST (Prince, Cool Crocks, Manhunter, ....)

I've successfully fitted 32 kB or CGA BRAM into CYC1000 FPGA which is a 42€ FPGA that happens to have approximately the same BRAM and Logic elements than MiST board.

I have infered the 8088 ROM into logic elements so that way I could use the free BRAM to add 16 kB more for CGA which allows some Tandy games to be played. Adlib music has been disabled because I had not enough logic cells.

CYC1000 FPGA used resources: LE 23953 / 24624 (97%). Memory blocks M9Ks 55 / 66 (83 %)
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

I'm in two fronts right now on the DeMiSTify ports:
  • Composite real video output
I'm still having issues with getting OSD to work in sync.
Currently I have two ways of outputting real composite:
- Through the Green Pin of the VGA connector (minimum 4 bits (maybe 3) are needed for the resistors DAC to output image in sync).
- Through one or two pins from GPIO. This method is simultaneous with the main CGA video, so you could have CGA output through VGA connector (or HDMI) and Composite video at the same time from a GPIO pin. This method from @TheSonders uses an IP serializer to achieve a PWM, obtaining a three-bit DAC with a single pin.

The minimum additional component to not damage the TV is to put a 200 Ohm resistor in series from the output pin (Green VGA pin or GPIO pin).

I know the MiSTer core has also a simulated composite video mode, but would be worth porting any of these methods to the MiSTer core ?
Where would the GPIO pin for the composite output be most appropriate to be allocated in MiSTer? User IO port maybe

https://github.com/somhi/PCXT_DeMiSTify ... omposite.v
  • Getting keyboard to work directly with the core and with the OSD without keyboard controller error
DeMiSTify don't support bidirectional communication with ps2 ports yet.
When connecting directly the keyboard into the core and into the DeMiSTify controller (for getting OSD) the keyboard eventually gets stuck (ps2 clk low I guess).

I think that the keyboard hung when the OSD is open and the core tries to send data out to the keyboard.

Dear @kitune-san, Is it possible that there might be a bug in the core's PS/2 component when the attached keyboard isn't responding ?

I could pass an intercept signal to the core when the OSD is open, so the core knows it and does not try to send out data to keyboard.

This port is the one which I'm testing with the core https://github.com/somhi/PCXT_DeMiSTify ... no_top.vhd
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

I did not envision any other devices intercepting between the keyboard and the PC core.
Indeed, the keyboard controller could stop if it intercepts during transmission.
I will put a timeout process in the transmit logic.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

However, there are few times when the PC transmits data.
Would the same problem occur if you open the OSD after DOS has booted?
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

kitune-san wrote: Tue Oct 18, 2022 12:07 am I will put a timeout process in the transmit logic.
Could you try this patch?
https://github.com/kitune-san/PCXT_DeMi ... 6cee64c85a
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Tue Oct 18, 2022 12:23 am However, there are few times when the PC transmits data.
Would the same problem occur if you open the OSD after DOS has booted?
It still happens but it is after loading the BIOS that the keyboard dies.
I don't know why some BIOS reset the core after loading while others don't (diagnostic BIOS do it).
The ruud diagnostic BIOS is the more likely to freeze the keyboard after being loaded into SDRAM.

I've tried the new send data patch (thanks for it) but I'm still experimenting keyboard freezes.
Before I could have freezes with the OSD open while the BIOS was booting up the system.
Now it seems I only get freezes after loading some BIOS into SDRAM.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by jordi »

Did the OSD expects AT or XT commands?


The XT kb. generates 2 start bits, 8 data bits, make/break bit, and a stop bit. The AT kb. is 1 start bit, 8 data, 1 parity, and a stop bit.
The XT uses a make/break bit to indicate key up/down. The AT sends one byte for keydown and two bytes for keyup.
The XT keyboard scan codes have different values than then AT keyboard make/break codes (for corresponding key locations).
The XT keyboard doesn't accept any of the command strings accepted by the AT keyboard.
The XT keyboard is reset by fiddling the clock and data lines; the AT keyboard accepts a reset command string


"It used a 5-pin DIN connector consisting of a clock and data line, with the idle state being clock high (+5V) and data low (0V)."

When a key is pressed, the clock line goes low (0V) for 36us (microseconds). This is followed by 9 clock pulses, each of which is 12.5us low and 20us high (32.5us each). On the 10th rising edge the clock then stays high (+5V) until the next sequence. The data line meanwhile changes on the rising edge of the clock. There are 7 data bits (the last 2 are always low). This 32.5us clock period gives us approximately a 31 kHz bit rate.

From: http://dosdays.co.uk/topics/xt_vs_at_keyboards.php
More: https://github.com/tmk/tmk_keyboard/wik ... d-Protocol

Leds can't work as it didn't had leds.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

somhi wrote: Tue Oct 18, 2022 7:39 pm
kitune-san wrote: Tue Oct 18, 2022 12:23 am However, there are few times when the PC transmits data.
Would the same problem occur if you open the OSD after DOS has booted?
It still happens but it is after loading the BIOS that the keyboard dies.
I don't know why some BIOS reset the core after loading while others don't (diagnostic BIOS do it).
The ruud diagnostic BIOS is the more likely to freeze the keyboard after being loaded into SDRAM.

I've tried the new send data patch (thanks for it) but I'm still experimenting keyboard freezes.
Before I could have freezes with the OSD open while the BIOS was booting up the system.
Now it seems I only get freezes after loading some BIOS into SDRAM.
Does the keyboard freeze only when the OSD is opened?

If you don't open the OSD, can you use the keyboard without problems?

If the OSD is the trigger of the problem:
Each time data is read, the core sets ps2clk low.
This may be causing problems.
Inserting logic to ignore the ps2clockout output from the core while the intercept is asserted may improve the problem.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

kitune-san wrote: Wed Oct 19, 2022 12:09 am If the OSD is the trigger of the problem:
Each time data is read, the core sets ps2clk low.
This may be causing problems.
Inserting logic to ignore the ps2clockout output from the core while the intercept is asserted may improve the problem.
For example:

Code: Select all

PS2_KEYBOARD_DAT    <= '0' when ((ps2_keyboard_dat_out = '0') and (intercept = '0') ) else 'Z';
PS2_KEYBOARD_CLK    <= '0' when ((ps2_keyboard_clk_out = '0') and (intercept = '0') ) else 'Z';
ps2_keyboard_dat_in and ps2_keyboard_clk_in signal is not included in the condition.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Tue Oct 18, 2022 12:23 am Does the keyboard freeze only when the OSD is opened?
If you don't open the OSD, can you use the keyboard without problems?
OSD is set to hide right after pressing enter to load a new BIOS. This is the point where the keyboard freezes, when a new BIOS is loaded into memory (not all BIOS freeze the keyboard).

Yes at the first startup if I don't open the OSD the keyboard works well. If I open the OSD and the core sends out data, in the next reboot the core will show keyboard error and keyboard controller missing in diagnostics
kitune-san wrote: Wed Oct 19, 2022 3:11 am
kitune-san wrote: Wed Oct 19, 2022 12:09 am If the OSD is the trigger of the problem:
Each time data is read, the core sets ps2clk low.
This may be causing problems.
Inserting logic to ignore the ps2clockout output from the core while the intercept is asserted may improve the problem.
For example:

Code: Select all

PS2_KEYBOARD_DAT    <= '0' when ((ps2_keyboard_dat_out = '0') and (intercept = '0') ) else 'Z';
PS2_KEYBOARD_CLK    <= '0' when ((ps2_keyboard_clk_out = '0') and (intercept = '0') ) else 'Z';
ps2_keyboard_dat_in and ps2_keyboard_clk_in signal is not included in the condition.
I have already tried that code and it still hungs keyboard.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

What is the reboot procedure after loading bios?

Could you check if the chipset reset signal is output during reboot?
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

Also, One point of concern is whether the intercept signal is low when the keyboard hangs up.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Thu Oct 20, 2022 3:04 am What is the reboot procedure after loading bios?
Could you check if the chipset reset signal is output during reboot?
Also, One point of concern is whether the intercept signal is low when the keyboard hangs up.

After loading BIOS the procedure is to manually reset the core from OSD. I checked the reset and reset_cpu signals, and they did not go high after loading the BIOS. I thought it was doing a reset because I could already see an error message from the diagnostic BIOS just loaded on the MS-Dos screen.

When the keyboard is halted, signals ps2_kbd_clk_* are low. The intercept signal is also low because the OSD is closed at that point.

The thing is that is very difficult to debug with signaltap as I cannot have very long samples. I put the trigger when the intercept signal goes low, but at that point ps2_kbd_clk_* are high, but inmediatelly thereafter the keyboard freezes. Then I do a manual trigger and verified that ps2_kbd_clk_* are low.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

Does manual reset not output reset signals?
Is it possible to reset the core without using OSD? For example, buttons.
When the keyboard hangs, does the diagnostic indicate errors except keyboard? For example, interrupt(8259).
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