Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

somhi
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Fri Oct 21, 2022 3:36 am Does manual reset not output reset signals?
Is it possible to reset the core without using OSD? For example, buttons.
When the keyboard hangs, does the diagnostic indicate errors except keyboard? For example, interrupt(8259).
Manual reset from OSD outputs reset signals in signaltap.

Yes I have added OR condition to reset_wire which comes from a fpga button. When the keyboard hangs (*) , pressing this button results in that the core effectively resets itself, but it does not load the latest BIOS selected before hanging. For ruud_diagnostics, the screen goes out of sync and after a few resets boots again the default BIOS located on SD card (yuko st in my case). For Tandy rom, I can see the MEMORY SIZE = 640 message but thereafter loads again the default BIOS Yuko ST.

(*) I can say now that when keyboard hangs, the core itself hangs. So when loading OS, If I load new BIOS the screen also freezes at the point where it was (e.g. countdown stops in the MS-DOS startup menu).

When keyboard hangs, diagnostic BIOS has not been loaded yet. See screen below.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

BIOS does not seem to be loading correctly.
Does neptuno use the ioctl_wait signal? if neptuno writes when this signal is high, it will not load correctly.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

Perhaps the time between when ioctl_download goes High and when it starts writing is too short.

As an experiment, I would like you to try the following reset conditions.
2022-10-22 121110.png
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

ioctl_wait signal is not present in MiST framework, so it is not in DeMiSTify also.

Yeah you were right, adding that condition in the reset signal now BIOS are being loaded correctly. Need to avoid the automatic reset though.

Some issues still facing:
- sometimes I'm still getting the keyboard controller error after flashing the FPGA
- OSD cannot be loaded always when required with OSD key because during some POST BIOS intervals the ps2_clk is low. Alternatively OSD can be loaded by a FPGA button.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

somhi wrote: Sat Oct 22, 2022 9:16 am Need to avoid the automatic reset though.
What is the reason for that?
somhi wrote: Sat Oct 22, 2022 9:16 am Some issues still facing:
- sometimes I'm still getting the keyboard controller error after flashing the FPGA
Even in the case of Mister, typing on the keyboard during keybord diagnostics will result in an error.
After resetting, does the error still occur when you take hand off the keyboard?
somhi wrote: Sat Oct 22, 2022 9:16 am Some issues still facing:
- sometimes I'm still getting the keyboard controller error after flashing the FPGA
- OSD cannot be loaded always when required with OSD key because during some POST BIOS intervals the ps2_clk is low. Alternatively OSD can be loaded by a FPGA button.
Could you try this?
https://github.com/kitune-san/PCXT_DeMi ... 38d7905023
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Thanks kitune-san! Your awesome :)

With your new commit I haven't experimented keyboard freezes any more. I can open the OSD any time during the POST.

It is Ok to have a reset everytime a BIOS is loaded.
Before I was used to load ECOO BIOS and PCXT BIOS and then manually reset, but I see no problem in getting used to the new way: load EC00 + automatic reset, then load PCXT BIOS and automatic reset.

When I get keyboard controller error it is difficult to go away with it. It's not enough with a reset signal, and sometimes not even with a reflash of the FPGA or a poweroff.

It is kind of aleatory to receive a keyboard error during startup. Just of a 5 consecutive power off tests, I got 3 OK and 2 keyboard errors.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Regarding original IBM5160 BIOS I always had keyboard problems before, that made that BIOS unusable for the DeMiSTify ports.
With the new keyboard attached directly to core I've been able to load this BIOS a few times without keyboard problems which is great, but most of the times I try this BIOS it still show errors. It beeps when I press the key, and sometimes the three keyboard lights are blinking continously.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

If the keyboard is reconnected, will the error be cleared?

I inserted 2-stage F/F into the input. If you are experiencing instability problems due to metastables, this may help.
https://github.com/kitune-san/PCXT_DeMi ... 031d4bb6b3
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Sun Oct 23, 2022 7:56 am If the keyboard is reconnected, will the error be cleared?

I inserted 2-stage F/F into the input. If you are experiencing instability problems due to metastables, this may help.
https://github.com/kitune-san/PCXT_DeMi ... 031d4bb6b3
None of both tests improves the situation, so I'm still getting half of times keyboard error message on Yuko ST POST.

I rolled back to a previous version without the latests changes on PCXT HDL where I was getting keyboard hangs and I see I'm not getting those aleatory message errors. I will try to implement changes one by one and see where the error messages appear.
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Continues from previous post:

Firstly, I enabled changes fron KFPS2KB.sv. No message errors and no hangs, but you have to wait until some POST operations finish to be able to open the OSD

Then I enabled change in Peripherals.sv (ps2_clock_out = ps2_send_clock;). No message errors and no hangs. This change let me open the OSD freely during POST.

Until here, I could reproduce a few times the problem with the IBM5160 BIOS. If I start BIOS at 14 MHz lights start blinking and keyboard doesn't work anymore. Starting BIOS at 4.77 MHz and changing it thereafter during the RAM test to 14.3 MHz let me work in this BIOS without keyboard problems.

Finally, I enabled changes from KFPS2_Send_Data, and it started appearing the aleatory keyboard message errors. The IBM BIOS is having keyboard problems again with this change, even with the procedure commented above.

So I definitely I will not apply changes from KFPS2_Send_Data as without it now all seems to be working Ok!
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Added Terasic DE10-lite port.

Currently ported FPGA platforms::

* Altera Max 10:
- Terasic DE10-lite
- Arrow Terasic DECA
* Altera Cyclone III: MiST, MiSTica
* Altera Cyclone IV:
- NeptUNO (Qmtech EP4CE55)
- UAreloaded (Qmtech EP4CE55)
- SiDi (ManuFerHi EP4CE22)
* Altera Cyclone V: Arrow Terasic SoCkit
* Altera Cyclone 10 LP: Trenz CYC1000 with Atlas carrier board
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Updated ports to Cyclone III & IV boards. https://github.com/somhi/PCXT_DeMiSTify

To-do list:
-8-bit IDE module implementation
-Floppy implementation
-RTC implementation
-Simulated composite implementation (note that is available real composite instead)-
-Border (overscan)
-Saving OSD configuration

somhi wrote: Tue Nov 01, 2022 8:02 pm

Added Terasic DE10-lite port.

Currently ported FPGA platforms::

  • Altera Max 10:
    • Terasic DE10-lite
    • Arrow Terasic DECA
  • Altera Cyclone III: MiST, MiSTica
  • Altera Cyclone IV:
    • NeptUNO (Qmtech EP4CE55)
    • UAreloaded (Qmtech EP4CE55)
    • SiDi (ManuFerHi EP4CE22)
  • Altera Cyclone V: Arrow Terasic SoCkit
  • Altera Cyclone 10 LP: Trenz CYC1000 with Atlas carrier board
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

Status of the non MiSTer ports:

In general, there seems to be some timing problems that can be seen on some BIOS and some boards where keyboard beeps with repetitive keypresses or not working at all (e.g. 5160 BIOS at CPU speed 9.54 or higher).

The most important point of the TO DO List is to implement the IDE and FDD.
MiSTer solution for IDE and FDD implementation is based on ao486 core which is hightly dependant on MiSTer main (Linux).
A solutions for IDE and FDD is needed for all non MiSTer ports, because currently the only way to load OS into the core is by means of an USB-Serial cable attached to a host computer serving an image with XTIDE serdrive program.

There is an interesting thread on how to implement the IDE https://atari-forum.com/viewtopic.php?t=42465

I would like to ask to Mr. @kitunesan if he could help with either of the constraints problem or the IDE / FDD implementation.
Do you have dear Kitune-san any other FPGA board apart from MiSTer where I could port the core to?

kitune-san wrote: Thu Dec 08, 2022 12:57 pm
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

I do not own any of the boards listed above. Nor do I know the details of each board.
Hence I hope the following information will help you.

I have wired the IDE for MiST using the code in the following link.
https://github.com/mist-devel/mist-modu ... ster/ide.v
https://github.com/gyurco/Next186/blob/ ... ST.sv#L372

I have not done any detailed research or debugging, so it will not work well as is.

Code: Select all


//
// XT2IDE
//
logic   [7:0]   xt2ide0_data_bus_out;
logic           ide0_cs1fx;
logic           ide0_cs3fx;
logic           ide0_io_read_n;
logic           ide0_io_write_n;
logic   [2:0]   ide0_address;
logic   [15:0]  ide0_data_bus_in;
logic   [15:0]  ide0_data_bus_out;

XT2IDE xt2ide0 (
    .clock              (clock),
    .reset              (reset),

    .high_speed         (0),

    .chip_select_n      (ide0_chip_select_n),
    .io_read_n          (io_read_n),
    .io_write_n         (io_write_n),

    .address            (address[3:0]),
    .data_bus_in        (internal_data_bus),
    .data_bus_out       (xt2ide0_data_bus_out),

    .ide_cs1fx          (ide0_cs1fx),
    .ide_cs3fx          (ide0_cs3fx),
    .ide_io_read_n      (ide0_io_read_n),
    .ide_io_write_n     (ide0_io_write_n),

    .ide_address        (ide0_address),
    .ide_data_bus_in    (ide0_data_bus_in),
    .ide_data_bus_out   (ide0_data_bus_out)
);


//
// IDE
//
logic           ide0_command_cs;
logic           ide0_control_cs;
logic           ide0_io_read;
logic           ide0_io_read_1;
logic           ide0_io_write;
logic           prev_ide0_io_read;
logic           prev_ide0_io_write;
logic [15:0]    ide0_writedata;


assign ide0_command_cs  = ~ide0_cs1fx;
assign ide0_control_cs  = ~ide0_cs3fx & &ide0_address[2:1];
assign ide0_io_read     = ~ide0_io_read_n  & (ide0_command_cs | ide0_control_cs);
assign ide0_io_write    = ~ide0_io_write_n & (ide0_command_cs | ide0_control_cs);

always_ff @(posedge clock)
begin
    ide0_io_read_1          <= ide0_io_read;
    prev_ide0_io_read       <= ide0_io_read_1;
    prev_ide0_io_write      <= ide0_io_write;
    ide0_address_1          <= ~ide0_control_cs ? {1'b0, ide0_address} : {1'b1, ide0_address};
    ide0_writedata          <= ide0_data_bus_out;
end


ide ide (
    .clk(clock), // system clock
    .clk_en(1'b1),
    .reset(reset),

    // cpu interface
    .address_in(ide0_io_read && ide0_address_1 == 4'hE ? 3'd7 : ide0_address_1[2:0]),
    .sel_secondary(1'b0),           // ? Research needed.
    .data_in(ide0_writedata{[7:0], ide0_writedata[15:8]}),    // ? 
    .data_out({ide0_data_bus_in[7:0], ide0_data_bus_in[15:8]}),     // ? 
    .rd(ide0_io_read   & ~prev_ide0_io_read),
    .hwr(~ide0_io_write & prev_ide0_io_write),
    .lwr(~ide0_io_write & prev_ide0_io_write),
    .sel_ide(ide0_command_cs | ide0_control_cs),
    .intreq(),          // ? Probably not used in PIO mode
    .intreq_ack(1'b0),  // ? Probably not used in PIO mode
    .nrdy(),
    .hdd0_ena(2'b10),        // ? Research needed.
    .hdd1_ena(2'b11),        // ? Research needed.
    .fifo_rd(),
    .fifo_wr(),

    // io controller interface
    …

It would be difficult to create a unified IDE/FDD controller for all boards.
The method of accessing HDD or FDD images differs from board to board.
Therefore, different approaches may be needed for different boards.

The first is to use a hard CPU within the FPGA. This is the same method as the MiSTer. Probably the same for MiST.

Second, use a software core such as NiOS II; boards using Intel FPGAs may share the same design.

Third, get the XT and IDE buses out of the FPGA board world and use the power of the vintage boards out there.
This is the only way to use FPGAs with small resources.
MiSTer PCXT reproduces the XT bus; the XT2IDE is just an FPGA emulation of the XT-IDE board, so it should be able to connect to a real IDE. (I haven't tried it...)
You may need some buffer circuitry, but it should be possible.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote:

It would be difficult to create a unified IDE/FDD controller for all boards.
The method of accessing HDD or FDD images differs from board to board.

Could the secondary SD of the MiSTer I/O board via SPI be used?

https://github.com/MiSTer-devel/Wiki_Mi ... ry-SD-card

It would be accessing the SD directly, without an HDD image in between, but it would be a step forward. Many of the FPGAs could access it this way in principle, it would already be better than having to use serdrive, and this would facilitate the port to these.

If this is done, the PCXT core could be added to the first list of this wiki entry:

Secundary SD.png
Secundary SD.png (15.29 KiB) Viewed 4797 times

You can also download the sources of any of these cores to check how the implementation has been carried out in MiSTer, and take it into account.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

I'll have to research the cores listed there, but if these are simulating IDE or FDC, it might be easy to port them.

...Or create an SPI device in HDL and create a driver (like universalbios).

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote: Tue Feb 07, 2023 2:32 pm

I'll have to research the cores listed there, but if these are simulating IDE or FDC, it might be easy to port them.

...Or create an SPI device in HDL and create a driver (like universalbios).

In case you can help...

https://opencores.org/projects/ata

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

Accessing the SD card itself is not difficult.
I have tried it myself. It was my goal to implement it on my PCXT.

https://github.com/kitune-san/KFMMC

The difficult part is how to create a wrapper for the FDC or IDE...

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote: Tue Feb 07, 2023 3:07 pm

Accessing the SD card itself is not difficult.
I have tried it myself. It was my goal to implement it on my PCXT.

https://github.com/kitune-san/KFMMC

The difficult part is how to create a wrapper for the FDC or IDE...

spark2k06 wrote: Tue Feb 07, 2023 2:43 pm
kitune-san wrote: Tue Feb 07, 2023 2:32 pm

I'll have to research the cores listed there, but if these are simulating IDE or FDC, it might be easy to port them.

...Or create an SPI device in HDL and create a driver (like universalbios).

In case you can help...

https://opencores.org/projects/ata

Wouldn't this help?

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

First, I will research the MXS and X68000 implementations.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

spark2k06 wrote: Tue Feb 07, 2023 3:10 pm
kitune-san wrote: Tue Feb 07, 2023 3:07 pm

Accessing the SD card itself is not difficult.
I have tried it myself. It was my goal to implement it on my PCXT.

https://github.com/kitune-san/KFMMC

The difficult part is how to create a wrapper for the FDC or IDE...

spark2k06 wrote: Tue Feb 07, 2023 2:43 pm
kitune-san wrote: Tue Feb 07, 2023 2:32 pm

I'll have to research the cores listed there, but if these are simulating IDE or FDC, it might be easy to port them.

...Or create an SPI device in HDL and create a driver (like universalbios).

In case you can help...

https://opencores.org/projects/ata

Wouldn't this help?

うーん、maybe.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Tue Feb 07, 2023 2:10 pm

I do not own any of the boards listed above. Nor do I know the details of each board.
Hence I hope the following information will help you.
...
It would be difficult to create a unified IDE/FDD controller for all boards.
The method of accessing HDD or FDD images differs from board to board.
Therefore, different approaches may be needed for different boards.

The first is to use a hard CPU within the FPGA. This is the same method as the MiSTer. Probably the same for MiST.

Thanks Kitune-san!

If you happen to own any other Altera board apart from MiSTer it would be easy to add it to DeMiSTify as a new target, so let me know if that's the case.

The good thing all PCXT non-MiSTer cores is that all share a common framework (DeMiSTify) which is a lite version on the MiST framework (not all functionalities are implemented as it is focused on boards with small resources). The way DeMiSTify works is like a MiST FPGA but instead of an ARM cpu it has a softcpu called EightThirtyTwo from Alastair M.Robinson.

Thanks for the tips. I'm sure they would be very handy.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

spark2k06 wrote: Tue Feb 07, 2023 2:21 pm
kitune-san wrote:

It would be difficult to create a unified IDE/FDD controller for all boards.
The method of accessing HDD or FDD images differs from board to board.

Could the secondary SD of the MiSTer I/O board via SPI be used?

https://github.com/MiSTer-devel/Wiki_Mi ... ry-SD-card

It would be accessing the SD directly, without an HDD image in between, but it would be a step forward. Many of the FPGAs could access it this way in principle, it would already be better than having to use serdrive, and this would facilitate the port to these.

If this is done, the PCXT core could be added to the first list of this wiki entry:

Secundary SD.png

You can also download the sources of any of these cores to check how the implementation has been carried out in MiSTer, and take it into account.

I am implementing an IDE-MMC(SDCard) conversion...

2023-02-23 224752.png
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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

kitune-san wrote: Thu Feb 23, 2023 2:03 pm

I am implementing an IDE-MMC(SDCard) conversion...

2023-02-23 224752.png

It looks great! This opens the door to other FPGAs

Great work, as always ;)

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

spark2k06 wrote: Thu Feb 23, 2023 2:16 pm
kitune-san wrote: Thu Feb 23, 2023 2:03 pm

I am implementing an IDE-MMC(SDCard) conversion...

2023-02-23 224752.png

It looks great! This opens the door to other FPGAs

Great work, as always ;)

It is now possible to recognize media sizes larger than 528 MB. :D
I will implement the READ/WRITE SECTORS command after tomorrow.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by flynnsbit »

Just don't run the dir command with all that space without FREESP running ;)

https://github.com/ChartreuseK/FREESP

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

memorandum:
Some ports on the SD card require pull-up resistors.
If pull-up resistors are not connected out of FPGA, they must be set up in Pin Planner.
My design requires pull-up resistors on the CMD and DAT[0] ports.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by spark2k06 »

flynnsbit wrote: Fri Feb 24, 2023 1:10 am

Just don't run the dir command with all that space without FREESP running ;)

https://github.com/ChartreuseK/FREESP

MSDos 6.22 and earlier support only FAT16, so the most we'll have to wait for will be the first dir command if 2Gb partition without FREESP.

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by kitune-san »

I created a new topic.

viewtopic.php?t=6204

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Re: Extend PCXT Development to Improve MiSTer Core (DeMiSTify Ports)

Unread post by somhi »

kitune-san wrote: Thu Feb 23, 2023 2:03 pm

I am implementing an IDE-MMC(SDCard) conversion...

For DeMiSTify ports the soft controller already uses SD card. Usually we don't have a secondary SD card like MiSTer does.
For testing purposes can be added a secondary SD card, but in MiST / DeMiSTfiy should be used a more integrated way to deal with the IDE. Do you think It is still valid the code you pointed to me some posts above ?

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