Help Needed Compiling Xain'd Sleena

[Fpg-lee]

Hi I get these errors when compiling Xain sleena..
I used Quartus lite 17.1 with Cyclone V qdz no external USB driver installed, just Quartus standalone and Cyclone plugin.

Can anyone help?

Thanks.



Error (10054): Verilog HDL File I/O error at SRAM_sync_init.v(21): can't open Verilog Design File "xs_desert_bgram1.bin_vmem.txt"
Error (12152): Can't elaborate user hierarchy "emu:emu|XSleenaCore:xlc|XSleenaCore_BACK1:xs_back1|SRAM_sync_init:ic121"
Info (144001): Generated suppressed messages file C:/Mister SD temp mount/XSleenaCore_MiSTer_Release-main/XSleenaCore_MiSTer_Release-main/output_files/Arcade-XSleenaCore_120SDR_ONLY_TILES.map.smsg

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 19 warnings
Error: Peak virtual memory: 6415 megabytes
Error: Processing ended: Wed Nov 23 17:40:36 2022
Error: Elapsed time: 00:00:39
Error: Total CPU time (on all processors): 00:00:25
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 19 warnings

[jca]

Posting a link to the project would be a good start, don't you think?

[Fpg-lee]

Hey all I did was load the Xsleena Qpf file from the Github source into Quartus and attempted to compile, then copied the error text.
How do I do that?

cheers.

[Flandango]

What Jca is asking is a link to were you downloaded the source code from so folks can take a look at it and see if they can help you with that error.

[Fpg-lee]

Oh here it is.

https://github.com/RndMnkIII/XSleenaCore_MiSTer_Release

[wark91]

I think you need to use this qsf file Arcade-XSleenaCore.qsf and not this one Arcade-XSleenaCore_120SDR_ONLY_TILES.qsf

Thanks

[Fpg-lee]

Hi Im new to compiling, do I still load the qpf file?
As loading the qsf file gives no option to compile..
Thanks again.

[wark91]

On the QPF file, you have two projects

# Revisions

PROJECT_REVISION = "Arcade-XSleenaCore_120SDR_ONLY_TILES"
PROJECT_REVISION = "Arcade-XSleenaCore"

Maybe you can comment this line "PROJECT_REVISION = "Arcade-XSleenaCore_120SDR_ONLY_TILES"" to be sure the second one is used.

[jca]

You can go to Project->Revision and change the revision used but it gives the same errors.
The core should be released in the next few days, I would wait.
https://www.youtube.com/watch?v=gkTlaAuJ4JM

[Flandango]

You won't be able to compile it at the moment because there are missing file(s).

[Fpg-lee]

Thanks for the help guys, yes I realized there was missing files, the compiler flagged that I couldn't locate from Github.
I may just buy Francisco a Kofi..
It was fun tinkering none the less.

[RndMnkIII]

Hi, sorry, while doing file cleanup in the release version I deleted some memory initialization files used by the code. They're not really needed anymore, but it's easier to add them to the repository to avoid errors in the synthesis process. I just uploaded said files to the repository, it should now synthesize with no problems.
This code is in beta, which means that I will probably add, modify and remove things during the development process.
You should clone the proyect from the github repo and from Quartus 17.0.x open the proyect (the Arcade-XSleenaCore.qpf). By default is active the revision Arcade-XSleenaCore_120SDR_ONLY_TILES. Compile it and voilá!

Just cloned from repo and synthesis run results:

captura_xain_core_synthesis_ok.png (142.59 KiB) Viewed 7569 times