MiSTer FPGA Forum

How many cycles (max) does it take to read the DDR Ram ?

looking at some cores they set the required address, set the read and then wait for read ready, but since I need to read 32 bytes per frame I would like to make sure I leave plenty of cycles to get the data I request returned. (and they won't all be in a row, it will jump about a bit) so I can time slice it nicely across them.

also does it need to be clocked at any specific speed ?

cheers

There is no max cycles for DDR. It depends on DDR business. 32bytes per frame you will be able to read in any case.
You supply clock to DDR3 bridge. No specific requirements.

with the frame buffer now being in DDRAM, can we still use DDRAM in the core as well ?

if so, do we need to be using it in when HBLANK and/or VBLANK is 1 to avoid conflict with FB ?

basically I want to use DDRAM for samples, but would like to keep up with latest SYS if possible. (and if I leave FB out of the QSF then it does not rotate for HDMI)

There is no difference in work from DDR access point of view. Even in non-FB mode DDR3 is used as buffer for video data.